High Speed Wireless Packet Communications

Research in this area is motivated by the need for an efficient, high speed, physical layer interface for applications such as broadband fixed wireless access (1-30 Mbps in macro-cellular environments) and high speed wireless LANs (20-100 Mbps in micro-cellular environments). A multidisciplinary effort focusing on communication system design, VLSI ASIC design and testbed development for high speed applications has already enabled our team to demonstrate 30 Mbps wireless data communications with uncoded BER < 10-7. We are currently looking at hardware and system solutions to effectively combine smart antenna arrays with adaptive equalization and low over head packet mode communications. Our current activity in this area are as follows:

System Design:

(a)  Development of techniques for low overhead, high bit-rate packet transmission using adaptive equalization and smart antenna arrays.

(b)  Design of high speed asymmetric systems requiring the implementation of adaptive equalization and beamforming at the base station for both uplink and downlink communications.

VLSI ASIC Design:

(a) Design of fully integrated VLSI baseband processors operating at high symbol rates (up to 10 Mbaud) and integrate the circuits for adaptive beamforming, adaptive equalization, variable symbol rates, variable QAM constellation sizes and fast frequency hopping.

(b)  Reconfigurable VLSI architectures and circuits for high speed (up to 30 MBaud) data communications.

(c)  Antenna Array processor for use in large smart antenna systems.

Testbed Development & Field Experiments:

Board level integration of developed ASICs into functional prototype testbeds complete with a host of user defined configurations. A user-friendly PC interface provides real-time information about the internal state of the transceiver. The first generation testbed has been used in several field trials to demonstrate the feasibility of 30 Mbps wireless data transmission in typical indoor environments. Plans are under way for the development of second and third generation systems with enhanced capabilities.

 

First Generation UCLA Testbed  (In Collaboration with Henry Samueli)

Demonstrated 30 Mbps Wireless Transmission with BER < 10-7

Highly versatile 5-MBaud equalized M-QAM Testbed features:

bullet Full speed (once every symbol) adaptation of all equalizer taps
bullet Variable constellation size
bullet Variable equalizer span
bullet Real time observation of
bullet equalizer taps
bullet Slicer SNR

Control loops 


 Reconfigurable High Speed Communications Processor

 A single, highly versatile VLSI architecture capable of performing any one of the following functions.

bullet Direct Digital Frequency Synthesis
bullet Fine frequency control up to 30 MHz
bullet Adaptive Filtering
bullet 60 MBaud symbol rates
bullet DFT based Fourier Transforms
bullet 32-point DFT at 60 MHz
bullet Real & Complex filtering

64-tap real at 60 MHz

 

DiverQAM (In Collaboration with Henry Samueli)

Highlights

bullet Single-chip wireless baseband receiver ASIC
bullet Delivers 8 giga-operations per second
bullet 800 mW power consumption (estimated) at 3.3V
bullet 620,000 transistors, 45 mm2 in 0.6 mm CMOS

Features

bullet 1-4 channel adaptive antenna beamformer
bullet 24-tap adaptive decision feedback equalizer
bullet Any symbol rate from 625 kBaud to 10 MBaud

0-80direct digital frequency synthesizer

 

Asymmetric High Speed Wireless Communication system

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Highly sophisticated base station unit

bullet Uplink and downlink channel equalization
bullet Diversity
bullet Adaptation



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Last updated: 05/07/04.