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                                 Events Home   Upcoming Events   Seminar Series
                                 Workshops      PhD Defenses        Visitor Seminars     Faculty Lectures

2008-2009 Seminars by Visitors to the Department
(excluding speakers in the Seminar Series)

2008-2009     2007-2008

Nanoelectronics for low power high performance Logic Applications.

Wilman Tsai
Intel Corporation

Tuesday, April 14, 2009 at 2:00pm
Boelter 8500

Abstract
The continual Si CMOS device scaling according to Moore’s law will need revolutionary channel material beyond Si past 22 nm node in year 2013-2019. Potential candidate are carbon nanotubes (CNT), semiconductor nanowires, Ge and III-V materials, for future high-speed and low-power computation applications. These materials, in general, have significantly higher intrinsic mobility (either higher electron or hole mobility) than Si, and they can be potentially used to replace Si as the channel of the transistor for very high speed applications. Both CNT and semiconductor nanowires are formed using "bottom-up" chemical synthesis, and they currently suffer from the fundamental placement and positioning problem. On the other hand, Ge and III-V materials can be patterned into desirable device structures using conventional "top-down" lithographic and etch techniques. Ge exhibit 5-10x higher hole mobility and III-V materials have ~50-100x higher electron mobility than Si, The objective of this talk is to review current Si CMOS technologies and highlight the various opportunities and fundamental technological challenges of Ge and IIIV nanoelectronics, for potential future high-speed and low-power logic applications.