Advanced Channel Engineering for Thin Body Transistors

Speaker: Po-Yen Chien
Affiliation: Ph.D. Candidate - UCLA

Abstract: As transistor dimension kept scaling down, many challenges arises such as worse electrostatic control and higher variability. In order to address these issues, thin down body thickness is widely accepted and device structures such as FinFET and SOI are employed. Although FinFET has been adopted as main device structure by major foundries like Intel and TSMC in 20nm node and beyond, its analog performances like g_m and f_T are still lagging behind the bulk and SOI and prevent it from applying to SOC applications. In order to maintain the scaling trend, new materials and/or novel device design is needed. Therefore, channel engineering by using laterally composed with different electron affinities along the channel is proposed to show improved analog performance.

Besides thinning down body thickness, there are other methods to realize thin body and one of them is applying channel engineering by employing deeply retrograde doping profile (DRCP) in bulk device. The doping profile is designed such that it behaves like a thin body device while maintaining bulk device structure. The advantage of DRCP device is that it is relatively cheap and less complicated in terms of manufacturing than those device structures with physically thinner silicon body like FinFET and SOI. It is then instructive to understand whether DRCP device can deliver comparable device performance as FinFET and SOI in 20nm regime. The physics of DRCP device is investigated by TCAD simulation tools and compared with halo device (conventional bulk device) to show the origin of the superior performance. The device performances of bulk device, DRCP, FinFET and SOI are compared to show the capability of DRCP device.

The other approach to make thin body is to utilize 2D materials like TMDs as channel material of transistor owning to its ultra-thin body property. 2D materials such as MoS₂ and WSe₂ were extensively exploited recently for FET fabrication due to the good short channel effect control and potential superior carrier transport. Among these 2D materials, WSe₂ is particularly attractive since p-type doping has been achieved making it possible for depletion mode p-FET. However, lack of reliable doping technique makes the doping of the WSe₂ difficult to be accomplished. In this dissertation, WSe₂ doped by controllable W:Ta co-sputtering process and synthesized by post selenization is demonstrated. The material synthesis and characterization of WSe₂ are discussed. The transmission line method (TLM) structure is used to extract the sheet resistance and contact resistance with palladium contact. The MESFET is fabricated and the performance is discussed.

Biography: Po-Yen Chien received his B.S. degree from National Central University and M.S. degree from National Tsing Hua University. He is currently a Ph.D. candidate in Electrical Engineering at University of California, Los Angeles. His research interests include the device simulation of nanoscale MOSFET and process integration of 2D material channel transistors.

For more information, contact Prof. Jason Woo (woo@ee.ucla.edu) 

Date/Time:
Date(s) - May 31, 2016
10:00 am - 12:00 pm

Location:
E-IV Tesla Room #53-125
420 Westwood Plaza - 5th Flr., Los Angeles CA 90095