A New Calibration Technique for Pipelined ADC

Bibhu Datta Sahoo
Advisor: Prof. Razavi

Monday, December 8, 2008 at 1:30 pm
Engr IV Room 57-124

Abstract:
The design of high speed, high resolution analog-to-digital converters (ADCs) continues to present greater challenges as the device dimensions and supply voltages are scaled down. While generic issues such as capacitor mismatch provided the impetus for earlier calibration techniques, deep-submicron low-voltage technologies have made it increasingly difficult to realize high gain op amps, requiring additional calibration that corrects for gain error and nonlinearity. With the declining intrinsic gain of transistors, it is expected that the notion of fast settling, low-voltage, high-gain op amps will eventually become obsolete. This research introduces a calibration algorithm based on blind LMS that corrects for capacitor mismatch, residue gain error and op amp nonlinearity. Incorporated in a 12-bit pipelined ADC using an op amp with an open-loop gain of 25, the calibration leads to a measured SNDR of 62 dB at an input frequency of 91 MHz, the highest combination reported in the literature. Fabricated in 90-nm digital CMOS technology the ADC achieves a DNL of 0.78 LSB, an INL of 1.7 LSB.

Biography:
Bibhu Datta Sahoo received his B.Tech and MS degree in Electrical Engineering from Indian Institute of Technology, Kharagpur and University of Minnesota in 1998 and 2000 respectively. From 2000 to 2006 he was at Broadcom Corporation, Irvine where he was involved in custom high speed digital circuit design, CMOS imagers, and various high voltage circuits using standard low voltage CMOS transistors. Since, 2004 he has joined the PhD program at UCLA where he is involved in high speed data converter design.