Beyond Scaling – Teaching the Old Dog some New Tricks!

Subramanian S. Iyer
IBM Semiconductor Research and Development Center

Monday, April 28, 2008 at 1:00PM

54-134 Engineering IV Building
Refreshments Served

Abstract: While the semiconductor industry has been focused on the challenges of scaling, it has become quite apparent that one must take a broader view of delivering productivity and performance gains in this new regime of non-classical scaling. While transistor level and interconnect performance will continue to make strides through the innovative use of stress engineering, novel materials such as high k dielectrics in the front end and low k dielectrics and high conductivity interconnects in the backend, there is much more to be gained by addressing the issues of memory integration including three dimensional integration, , on-chip decoupling and autonomic chip functions.

The scaling of memory poses a very significant challenge as it is quickly becoming a dominant part of the chip real estate and easily exceeds 70% of the chip area and contributes immensely to processor performance. Till recently most of this memory was SRAM. But SRAMs have not scaled gracefully for several reasons and we have begun to use embedded DRAMs for fast dense memory. We will examine the tradeoffs and technological and design advances that have made this possible to use embedded DRAMs to replace large blocks of SRAM memory and are being used extensively in network switches and high performance computing such as the BlueGene® chip as the onboard cache. More recently, we have been able to integrate trench based eDRAM in high performance processor technology as well and show a significant improvement in DRAM performance through a combination of process technology, DRAM architecture and circuit design. However, even wit these innovations, on-chip memory is necessarily limited and it will be necessary to explore the third dimension

Trench base DRAM technology, also lends itself to some very novel decoupling solutions. Typically modern logic chips switch at rates of several GHz and at these frequencies there are significant transient voltage droops called voltage compression. The local collapse of the power grid on a chip can lead to unpredictable results including functional breakdown, and memory failure. We look at the ways in which trench based on-chip decoupling alleviates these problems. This allows a 25X increase in decoupling capacitance for the same area and this can result in an almost 5-8 % decrease in power or equivalently a corresponding improvement in performance. The innovative use of a simple passive element gives us half a generation advantage.

Finally, we have developed the concept of an electrical fuse based on electromigration that can be combined with on-chip built in test and repair system. This can be used for chip repair at wafer level, in the package and in the field, power management, Bill of Materials, Yield management and a host of autonomic functions as well as onetime programmable memory. We will explore these applications.

While scaling and innovative new materials will continue to provide density and performance improvements to CMOS technology, a judicious use of memory technologies, the innovative use of on chip structures such as trenches for decoupling and the innovative use of phenomena such as electromigration and three dimensional integration will continue to provide huge benefits in altogether new dimensions.

Biography: Subramanian S. Iyer is Distinguished Engineer and Chief Technologist for the Semiconductor Research and Development Center, IBM Systems & technology Group, and is responsible for setting semiconductor technology direction. Till recently he was Director of 45nm CMOS Development. He obtained his B.Tech in Electrical Engineering at the Indian Institute of Technology, Bombay, and his M.S. and Ph.D. in Electrical Engineering at the University of California at Los Angeles. He joined the IBM T. J. Watson Research Center in 1981 and was manager of the Exploratory Structures and Devices Group till 1994, when he founded SiBond LLC to develop and manufacture Silicon-on-insulator materials. He has been with the IBM Microelectronics Division since 1997. Dr. Iyer has received two Corporate awards and four Outstanding Technical Achievement awards at IBM for the development of the Titanium Salicide process, the fabrication of the first SiGe Heterojunction Bipolar Transistor , the development of embedded DRAM technology and the development of eFUSE technology. His current technical interests and work lie in the area of 3-dimensional integration for memory sub-systems and the semiconductor roadmap at 22nm and beyond. He holds over 40 patents and has received 19 Invention Plateau awards at IBM. He received the Distingushed Aluminus award from the Indian Institute of Technology, Bombay in 2004. Dr. Iyer has authored over 150 articles in technical journals and several book chapters and co-edited a book on bonded SOI . He has served as an Adjunct Professor of Electrical Engineering at Columbia University, NY. Dr. Iyer is a Fellow of IEEE and a Distinguished Lecturer of the IEEE.