Design and CAD Challenges for 45nm CMOS and Beyond

Ruchir Puri
IBM Research

Monday, March 3, 2008 at 1:00PM

54-134 Engineering IV Building
Refreshments Served

Abstract: With semiconductor industry's aggressive march towards 45nm CMOS technology and introduction of new materials and device structures in sight for 32nm and 22nm nodes, it is crucial for the IC design and CAD community to understand the challenges posed by these potential technology changes. This talk will focus on these challenges starting from front end of line (devices) to the back end of line (interconnects) and finally the impact on CAD. These advanced device and interconnect structures and materials including 3D technology have tremendous impact on the direction of the CAD industry. This talk will describe the design methodology and CAD implications of these imminent technology changes.

Biography: Ruchir Puri received M.Tech. degree in electrical engineering from Indian Institute of Technology (IIT), Kanpur, India in 1990, and a Ph.D. degree in electrical and computer engineering from University of Calgary, Alberta, Canada in 1994 where he received 1993 ACM/IEEE Design Automation fellowship. He joined VLSI Design Automation group at IBM Thomas J. Watson Research Center, Yorktown Heights, NY in 1995, where he manages a research group focused on Logic and Physical Synthesis. He has received many IBM awards for his work including Outstanding Technical Achievement awards, IBM Innovation awards, and IBM Execute Now award. He has also been an Adjunct Professor in Electrical Engineering at Columbia University, New York where he taught VLSI design and Circuits. He has served on program committees of most major VLSI Design Automation conferences, National Science Foundation and Semiconductor Research Corporation panels and has been an invited speaker at numerous conferences such as ISSCC, DAC, ICCAD. He is the inventor of over 25 U.S. patents and has authored over 85 publications on the design and synthesis of low-power and high-performance circuits. He currently serves as Associate Editor of IEEE Transactions on Circuits and Systems I and has served as Associate Editor of the Transactions on Circuits and Systems II. Dr. Puri is a member of ACM SIGDA Physical Design Technical Committee as well as Logic Synthesis Techincal Committee. He was honored as an ACM Distinguished speaker in 2006. Dr. Puri was elected an IEEE Fellow in 2006 for "contributions to automated logic and physical design of electronic circuits."