A CMOS Digital Phase-Locked Loop for Nanometer-Scale Technology

Ping-Hsuan Hsieh
Advisor: Chih-Kong Ken Yang

Tuesday, March 3, 2009 at 11:00am-1:00pm
Engr IV Room 57-124

Abstract:
Digital implementations of phase-locked loops (DPLLs) have emerged as an attractive alternative in nanometer CMOS process. We propose a DPLL design for clock generation in large digital systems. A 9-bit interpolator-based DCO is used for low jitter performance and wide operating frequency range. The use of an integer divider in the loop filter greatly relaxes the trade-off between the steady-state dithering jitter and the resolution requirement on the DCO. The phase selection is based on a token-passing technique with an asynchronous control block using self-reset circuits to speed up the operation and to reach GHz of operation. With the ability to dynamically sweep the output frequency from 3.5MHz to 1.8GHz, the proposed design is suitable for DVFS and spread-spectrum I/O applications. Bandwidth-tracking ability is achieved with the use of replica delay line in the PD. Without calibration, the empirical results show a near constant damping factor and a bandwidth that tracks with the reference frequency across different operating conditions. The prototype is designed and implemented with 65nm CMOS technology with the core area of 800x700m2 and consumes 220mW at 1.6GHz with the measured rms/pp jitter of 2.63/22.2ps.

Biography:
Ping-Hsuan Hsieh received her B.S. degree in electrical engineering from National Taiwan University in 2001. Since 2001, she has been with the University of California, Los Angeles, where she is working toward her Ph.D. in the area of integrated circuits and systems. She was an intern at Texas Instruments in summer 2004, 2005 and 2006 as part of the funding program for her Ph.D. study. Currently her research interests include analog and digital Phase-Locked Loop circuit designs.