A MIMO decoder accelerator for next generation wireless communications

Karim Mohammed
Advisor: Babak Daneshrad

Tuesday, March 17, 2009 at 4:00pm-6:00pm
Engr IV Room 67-124

Abstract:
Multi antenna, MIMO techniques have been recognized as the next revolution in wireless communications. In fact many current and emerging wireless standards for WiFi, WiMax, and cellular have written MIMO into their requirements. Additionally, all trends point to the convergence of all such wireless standards on a single platform such as a PDA or smartphone. This motivates a highly programmable accelerator-like approach that can efficiently deliver the required processing power to enable implementation of current and future algorithms within the framework of any wireless communication system.

MIMO decoding in high throughput systems involves dedicated implementations that support a small set of algorithms and antenna configurations. More flexible solutions use general purpose processors, with more limited performance. We present a novel MIMO decoder accelerator architecture that provides a level of flexibility in matrix operations approaching that of a DSP while maintaining a much higher performance-cost metric. The accelerator features a Harvard-like architecture with complex vector operands and a deeply pipelined fixed-point complex arithmetic processing unit. The processing unit includes a programmable coordinate rotation core, and a multiple-cycle dynamic scaling circuit. A novel memory map uses properties of matrix operations in OFDM to simplify addressing while allowing single cycle access to arbitrarily arranged vector operands. An OFDM based processing cycle allows the processing core to be continuously engaged, and removes the overhead of instruction fetching. The accelerator, the machine level instruction, and the associated compiler are scalable in processor port size, data memory size, word length, and memory access scheme. When implemented on a Xilinx Virtex-4 LX200FF1513 FPGA, the design occupied 43% of overall FPGA resources. The accelerator shows an advantage of up to three orders of magnitude in power-delay product relative to a general purpose DSP for a range of complex matrix arithmetic operations, matrix decompositions, and MIMO decoding algorithms.

Biography:
Karim Moahmmed was born in Giza, Egypt. He received his B.Sc. and M.Sc. in Electrical Engineering from Cairo University, Cairo, Egypt in 2002 and 2004 respectively. In 2004 he joined the Wireless Integrated Systems Research lab (WISR), UCLA where he has been working towards his Ph.D.