Multi-Gb/s communications at 60GHz: Radio architecture and circuit design

Yorgos Palaskas
Intel Corporation

Monday, February 23, 2009 at 1:00PM
54-134 Engineering IV Building
Refreshments Served

Abstract: This presentation reviews recent developments in 60GHz radio design based on research at the Communications Circuits Lab of Intel. The talk starts with an overview of systemlevel requirements for high rate OFDM radios as dictated by the tradeoffs between the different circuit blocks. Design considerations and experimental results are presented for some of the key blocks, namely the Analog-to-Digital Converter, Low-Noise Amplifier, and Frequency Synthesizer. We report techniques for bandwidth extension, calibration, and time-interleaving for multi-GS/s Analog-to-Digital conversion required at 60GHz. We discuss the design and testing of Low Noise Amplifiers at mm-wave frequencies, using a fabricated 64GHz LNA as an example. Frequency synthesis at 60GHz is challenging due to phase noise limitations of the VCO and speed limitations of the frequency divider. We report on a fabricated 40GHz fractional-N synthesizer that uses an injection-locked divideby- 4 circuit that is automatically tuned for optimal performance. Finally, 60GHz radios might require phased-array techniques to cover distances desired for some key applications; the talk concludes with a discussion on the challenges associated with phased-array systems at 60GHz.