Optimization and Rapid Prototyping of Power-Limited Digital Systems

Professor Dejan Markovic
UCLA Electrical Engineering

Wednesday, May 13, 2009 at 1:00PM
54-134 Engineering IV Building

Refreshments Served

Abstract: Our ability to access increasing amounts of data while power-constrained has created a major shift in information technology towards parallel data processing. Today's microprocessors are deploying multiple cores to increase performance; wireless communication devices are using multiple antennas to transmit data faster and farther; new devices for processing large data records in bio-medical applications are needed. The fundamental challenge in all these applications is how to map parallel-data algorithms onto the underlying hardware technology while meeting application constraints for power density and performance.

This talk will address the issues of design productivity and complexity in power-limited digital systems. An optimization methodology that integrates algorithm and technology parameters will be presented to demonstrate automated generation of DSP architectures that are represented in energy-area-performance space for rapid system development. The optimization approach is formalized within a graphical high-level Matlab/Simulink description that nicely maps to both FPGA and ASIC platforms. The common design description also enables FPGA-assisted ASIC verification that leverages test vectors from the algorithm development.

The use of the design methodology will be exemplified on designs with diverse power, performance, complexity, and flexibility features. A complex multi-core sphere decoder suitable for systems with up to 16x 16 antennas will demonstrate flexibility for multi-mode operation with energy efficiency of dedicated designs. To illustrate extreme power-density levels, 64-channel neural-spike DSP will demonstrate ~ 20 μW/mm² power density and a 98.8% data compression for use in implantable many-channel neural recording and stimulation systems.

Biography