RF-Interconnect for Future Network-On-Chip

Sai-Wang (Rocco) Tam
Advisor: M-C. Frank. Chang

May 14, 2009 at 1:00pm-3:00pm
Engr IV Room 67-124

Abstract:
In the era of the nanometer CMOS technology, due to stringent system requirements in power and performance, microprocessor manufacturers are relying more on chip multi-processor (CMP) designs. CMPs partition Silicon real estate among a number of processor cores and on-chip caches, and these components are connected via an on-chip interconnection network (Network-on-chip). Since interconnects have been projected as the limiter in nanometer designs in terms of power and latency, the communication infrastructure would significantly impact the performance, area, and power of future CMPs. To mitigate this impact on future CMPs, we explore the use of RF-interconnect (RF-I) that can simultaneously communicate among multiple communication channels with reconfigurable bandwidth allocation, and yet provide low energy per bit.

First, we propose a micro-architectural exploration framework that can be used to facilitate the exploration of scalable CMP, particularly for CMPs with a large number of cores. In multi-band RF-I, a wide tuning range on-chip frequency synthesis approach is required to enable the simultaneous generation of multiple carrier frequencies. The design and implementation of two new approaches in multiple carrier frequencies generation, simultaneous sub-harmonic injection locking technique and the multi-band left-handed resonator technique, are described in this talk. Furthermore, a simultaneous tri-band on-chip RF-I for future network-on-chip is demonstrated. Two RF bands in mm-wave frequencies, 30GHz and 50GHz, are modulated using amplitude-shift keying (ASK), while the base-band utilizes a low swing capacitive coupling technique. Three different bands, up to 10Gbps, are transmitted simultaneously across a shared 5mm on-chip differential transmission line. Finally, we demonstrate that RF-I has dramatic potential in terms of low-latency, low-power and high-bandwidth operation, which are the keys for the future CMP.

Biography:
Sai-Wang (Rocco) Tam was born in Hong Kong. He received the B.Sc. and M.Sc. degree in electrical engineering from the University of California, Los Angeles. He is currently pursuing Ph.D degree at the same university, under the supervision of Professor M-C.Fank.Chang. Mr. Tam has held several summer intern positions at Intel Corporation microprocessors mixed-signal circuit group in 2004, 2005 and 2006. His research interests includes high speed mixed-signal circuits, MM-wave circuits (60 GHz or above), high speed A/D, RF-interconnect and network on chip. He is a student member of IEEE and Eta Kappa Nu.