Transmitter Linearization by Beamforming

ChuanKang Liang
Advisor: Behzad Razavi

Monday, November 23, 2009 at 10:00am
Engr IV Room 57-124

Abstract:
In order to increase the data rate in a communication link, the modulation scheme can incorporate a high-order constellation but at the cost of tighter linearity and/or phase noise requirements. For example, if QPSK is replaced with 16QAM, the data rate increases by a factor of 2 while the transmitter output level must be backed off by 6 to 8 dB even if adjacent channel power is not a concern.

Among various transmitter linearization techniques, two are based on signal decomposition and have shown promise for integration: polar modulation and outphasing. However, the former must deal with delay mismatches between the phase and amplitude paths and the leakage of the phase signal to the output, a serious issue at millimeter-wave frequencies. Outphasing faces two drawbacks: the loss due to the output power combining operation, especially if realized on-chip, and the undesirable coupling between two power amplifiers through the combiner.

This work describes a transmitter linearization technique that avoids the two issues of outphasing and is suited to beamforming arrays. Two or more constant-amplitude outphasing signals are transmitted by different antennas and combined in space, thus reconstructing the original amplitude and phase-modulated signals. The proposed approach provides a favorable trade-off between spectral and power efficiencies while avoiding loss and coupling effects present in conventional outphasing systems. Additionally, the directivity of the new approach translates to a narrow spatial angle for correct signal reception, yielding a high level of security. A dual-transmitter prototype fabricated in 65-nm CMOS technology and designed for the 60-GHz band produces a 16QAM output of +9.7 dBm with 11% efficiency and an EVM of -18.8 dB.

Biography:
ChuanKang Liang received her B.S. and M.S. degrees from Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University (NTU), Taiwan, in 2004 and 2006, respectively. Her M.S. thesis focused on the design and implementation of CMOS all-digital fast-locking DLL-based clock generators and won the Best Master Thesis Award of Taiwan IC Design Society in 2006. In Fall 2006, she joined the University of California, Los Angeles for her PhD program. Her research interests include the architecture and system design of high speed transceivers and RFICs for wireless communications. She has been a student member of IEEE since 2005.