Uncertainties Modeling and Statistical Optimization for Power Integrity of VLSI Circuits and Systems

Yiyu Shi
Advisor: Lei He

Tuesday, April 28, 2009 at 10:00am-12:00pm
Engr IV Room 57-124

Abstract:
The continuous scaling trends of smaller technologies, higher operating frequencies, lower power supply voltages, and more functionality for integrated circuits and systems have made it extremely challenging to design a reliable power delivery network (PDN): Design uncertainties, process uncertainties and operation uncertainties have to be considered during the modeling and optimization to guarantee the quality of the PDN's.

To model the design uncertainties, three reduced order modeling techniques for design sign-off, early design verification and design optimization respectively have been developed. The reduced models can be used for fast simulation with design changes. In addition, an incremental random walk algorithm is proposed for incremental and on-demand analysis of the PDN's. To model the process and operation uncertainties, a stochastic algorithm has been proposed to extract the process uncertainties and operation uncertainties in the current loads and form parameterized current models. Geared by those uncertainty models, we have further proposed novel algorithms to suppress two dominant types of the noise present in a PDN, the peak noise and the resonance noise, using decoupling capacitance (decap) and proactive frequency actuator respectively. Experimental results show that significant noise reduction is achieved.

Biography:
Yiyu Shi received his B.E. in electronic engineering with honor from Tsinghua University, China, P.R in 2005 and his M.S. in electrical engineering with honor from University of California, Los Angeles in 2007, where he is now a Ph.D. candidate. He has authored or co-authored over 20 journal and conference papers in the field of design automation, including five best paper finalists in Design Automation Conference 2006, 2009, International Conference on Computer-aided Design 2007, International Conference on Computer Design 2008 and Asia and South Pacific Design Automation Conference 2009. He received the IBM Invention Achievement Award in 2009 in recognition of his U.S. patent on multi-layer process space coverage for at-speed testing.