VLSI Architectures and Implementations of Iterative FEC Decoders

Tzu-Chieh Kuo
Advisor: Alan N. Willson, Jr.

Wednesday, May 20, 2009 at 10:00am-12:00pm
Engr IV Room 67-124

Abstract:
Forward error correcting (FEC) codes are essential parts of digital communications systems. In recent years, research interests have moved to advanced coding schemes such as turbo codes and low-density parity-check (LDPC) codes that use iterative decoding to achieve better performance. A decoder implementation for these advanced codes must be optimized at all aspects of its design phases in order to realize a competitive replacement for conventional codes. In this talk, we present the architectures and VLSI implementations of two iterative QC-LDPC decoders.

A low-complexity decoder chip that employs the efficient layered-decoding message-passing algorithm and the offset Min-Sum check algorithm for irregular QC-LDPC codes has been developed in 0.18-um CMOS. With sequential processing units, consolidated memory architectures and optimized computation scheduling, this programmable chip can decode all QC-LDPC codes in the Mobile WiMAX (IEEE 802.16e) standard for significantly reduced complexity. It achieves 68-Mbps decoding throughput with 55K logic gates, consuming 149.8 mW at 1.8V and 65 mW at 1.2V. The corresponding energy consumption per bit per iteration is 220 pico-Joule at 1.8V and 96 pico-Joule at 1.2V. Alternatively, a QC-LDPC decoder based on the delta-based layered-decoding message-passing algorithm has also been developed for high-throughput applications. It achieves 287-Mbps decoding throughput with an estimated power consumption of 836 mW from 1.8V for the WiMAX codes. Its energy consumption is 291 pico-Joule per bit per iteration.