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A 3MHz-BW 3.6GHz Digital Fractional-N PLL with Sub-Gate-Delay TDC, Phase-Interpolation Divider, and Digital Mismatch Cancellationi

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What
  • Visitor Seminars
When Jan 12, 2010
from 11:00 AM to 12:00 PM
Where Engr IV Maxwell Room 57-124
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Marco Zanuso
Politecnico di Milano, Italy

Tuesday, January 12, 2010 at 11:00am
Engr IV Maxwell Room 57-124

Abstract
A 3.6GHz digital fractional-N PLL combines a 4b TDC with digital element shuffling, and a 4b feedback phase interpolator with digital cancellation of mismatches. It achieves maximum in-band fractional spur of -57dBc and in-band noise of -104dBc/Hz at 400kHz offset with 3MHz bandwidth. The PLL draws 67mA from a 1.2V supply and occupies an active area of 0.4mm2 in 65nm CMOS.

Biography
Marco Zanuso, born in 1981, received the M.Sc. and the Ph.D. in Electrical Engineering from Politecnico di Milano (Italy) in 2005 and 2009. He is currently a Post-Doc researcher at Politecnico di Milano. His major research activity concerns frequency synthesis with particular emphasis on the design of hybrid analog/digital phase locked loops. He is co-author of three patents.

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