Energy-Efficient VLSI Signal Processing for Multi-Band MIMO Systems

Chia-Hsiang Yang
Advisor: Dejan Markovic

Tuesday, April 27, 2010 at 10:00am
Engr. IV Maxwell Room 57-124

Abstract:
MIMO communication has recently received significant attention due to its potential to increase link robustness and channel capacity. Complex signal processing and coding schemes are being deployed to improve spectral efficiency. Hardware realizations of complex MIMO algorithms are quite challenging, especially for large antenna array and constellation sizes. Application-specific design is one option for MIMO signal processing, but the convergence of a variety of applications and standards on a single device argues for a more flexible implementation. Scalable antenna array and constellation sizes are required to properly realize diversity and multiplexing gains. Another requirement for OFDM-based systems is the support of multiple sub-carriers.

To address the complexity, power-efficiency, and flexibility challenges, I will discuss hardware realization of MIMO sphere-decoding algorithm. The algorithm can approach maximum likelihood performance with acceptable computational complexity. Existing architectures are challenged by the increase in antenna array size and modulation size. For depth-first architectures, the number of processing cycles is too high; for K-best architectures, the search range is fixed without taking the advantage of tree pruning.

In this work, we propose a 16-core sphere decoder architecture that can resolve the limitations of the depth-first and K-best search methods. With the flexibility of back-trace and forward-trace for each core, the sphere decoder can speed up the search and improve the BER performance. The proposed architecture supports antenna arrays from 2×2 to 16×16, modulations from BPSK to 64-QAM, and 8 to 128 sub-carriers. A 16-core architecture achieves 3 GOPS/mW and 10 GOPS/mm2 in a 90 nm CMOS. The peak estimated data rate exceeds 1.5 Gbps over a 16 MHz channel. Extending the flexibility to multiple signal bands, we demonstrate an 8×8 3GPP-LTE compliant decoder with a 128-2048 FFT block and soft outputs in 3.35mm2, dissipating 13.83mW in a standard-VT 65nm CMOS technology. Operating at 160MHz, the chip provides a peak data rate of 960Mbps in the 8×8, 64QAM mode over a 20MHz channel. LTE specs are met with 5.8mW power for throughput of 480Mbps.

Biography:
Chia-Hsiang Yang received his B.S. and M.S. degrees from Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University (NTU), Taiwan, in 2002 and 2004, respectively. His research is focused on energy-efficient architectures and digital integrated circuits for biomedical and communication signal processing. He was a recipient of the 2010 DAC/ISSCC Student Design Contest Award. He has been a student member of the IEEE since 2007.