Multi-band RF Interconnect for Future Memory Interface

Gyungsu Byun
Advisor: Frank Chang

Tuesday, May 4, 2010 at 4:00pm
Engr. IV Maxwell Room 57-124

Abstract:
In this talk, novel lower energy-per-bit chip-to-chip communication techniques such as Off-chip Multi-band RF Interconnect (OMRF-I) circuit and design techniques for future advanced memory interface systems will be presented.

In the era of the nanometer CMOS technology, due to stringent system requirements in power and performance, microprocessor and memory manufacturers are relying more on multi-core processors and energy-efficient memory interface designs. Since the power consumption of chip-to-chip communication between CPUs and DRAMs has been projected as the key limiting factor in nanometer designs in terms of power and latency, the communication infrastructure would significantly impact the performance, area, and power of future memory interface. To mitigate this impact on future memory interface, we explore the use of RF-interconnect (RF-I) that can simultaneously communicate among multi-core CPUs and DRAMs with reconfigurable bandwidth allocation, and provide much lower energy per bit.

Furthermore, a simultaneous multi-band off-chip RF-I prototype chips for future advance memory interface are demonstrated using a CMOS 65nm process technology. One RF band in mm-wave frequency, 20GHz, is modulated using amplitude-shift keying (ASK), while the base-band utilizes the state-of-the-art circuit technique which is fully compatible to a standard DDR3 memory interface. Multi different bands, up to 10Gbps, are transmitted simultaneously across a shared 5cm off-chip transmission line. Finally, we demonstrate that RF-I has dramatic potential in terms of low-latency, low-power and high-bandwidth operation, which are the keys for the future memory interface.