Novel Asymmetric Tunneling Source Transistors for Energy Efficient Circuits and Mixed Signal Applications

Ritesh Atul Jhaveri
Advisor: Jason Woo

Thursday, June 10, 2010 at 2:00pm
Maxwell Room, 57-124 Engr. IV

Abstract:
Over the history of integrated circuits, a gargantuan increase in speed and performance has been achieved due to the trend of scaling. In recent years, however, many daunting challenges arise as we scale into sub-32nm regime. The building block of the MOSFET device, Silicon, is being pushed to its performance limitation. New materials and design methodologies are being investigated to extract better performance. In this study, we concentrate on two flavors of Novel Source Tunneling Transistors: the Schottky Tunneling Source FET and the Source Pocket band-to-band tunneling FET.

Schottky barrier FETs have recently attracted attention as a viable alternative to conventional CMOS transistors for sub-32nm technology nodes. In this study, an asymmetric Schottky Tunneling Source SOI FET (STS-FET) has been proposed. The STS-FET has the source/drain regions replaced with metal/silicide as opposed to highly doped silicon in conventional devices. The main feature of this device is the injection of carriers through gate controlled Schottky barrier tunneling at the source. The optimized device structure shows improved performance as compared to conventional schottky FETs. The analog performance of the STS-FET was studied and the device was found to be a superior alternative to conventional CMOS transistors. The STS-FET was then fabricated with NiSi technology and successfully demonstrated for 0.1µm gate lengths. The high immunity to short channel effects and the excellent analog performance of the device makes it an attractive candidate for continued scaling into sub 32nm node as well as mixed signal applications.

Energy Efficiency is an important concern for sub-32nm CMOS integrated circuits. Scaling of devices to below 32nm leads to an increase in active power dissipation (CVDD2.f) and off-state power (IOFF.VDD). Hence, new device innovations are being explored to address these problems. In this study, a novel source-pocket tunnel field effect transistor (TFET), based on the principle of band to band tunneling is studied. TFETs have the potential to overcome the 60mV/dec limit set on the subthreshold swing of conventional CMOS transistors thus making them very attractive for continued power supply scaling. p-i-n TFETs and source-pocket TFETs were studied, optimized and successfully demonstrated on both bulk and SOI substrates. The source-pocket TFET shows better performance when compared to a p-i-n TFET. The conclusion is that if multiple strategies are used to improve the device performance, the source pocket TFET along with other TFETs can be very attractive alternatives to conventional MOSFET devices especially for low power applications.

Biography:
Ritesh Jhaveri comes from a small town called Bombay. He received his B.Tech from Indian Institute of Technology, Bombay where his final year project involved working on pentacene and DNA based molecular electronics. During the summer of 2002, he interned at the Ecole Polytechnique Federale de Lausanne, Switzerland eating chocolates and working on MEMS devices, particularly micro gas ionizers. He is currently pursuing his Ph.D. degree at University of California, Los Angeles (UCLA) where the force has been with him. The primary focus of his research is a novel tunneling CMOS device design for energy efficient circuits and mixed signal applications. His research interests also include device design and process integration.