Planar Source Pocket Silicon Tunnel Field Effect Transistor: Potential Device Solution For Low Power Applications and Improving Tunneling MOSFET Performance

Venkatagirish N.
Advisor: Jason Woo

Tuesday, May 25, 2010 at 8:30am
Engr. IV Maxwell Room 57-124

Abstract:
Low operating power is a very important concern for sub-45nm CMOS integrated circuits. Scaling of devices increases the off state leakage (IOFF), active power dissipation and subthreshold power (IOFF.VDD). Supply voltage (VDD) scaling is an essential component to control power consumption. For conventional CMOS devices, VDD scaling is slowing down due to non-scalability of built-in potential. Thus, in recent years, there has been an increasing need to explore novel devices which can provide reduced power operation with speed comparable to Si CMOS devices. The new device structures need to achieve low leakage currents at low VDD and still maintain a high on-current (ION) to have switching speeds comparable to Si-CMOS technology. This puts a constraint on the minimum overdrive voltage required. The devices therefore need a lower threshold voltage while maintaining a low IOFF which is strongly dependent on the subthreshold swing (SS) of the device. This necessitates the need to break the diffusion limited 60mV/dec subthreshold swing barrier.

Tunneling FETs have been theoretically shown to exhibit a steep subthreshold swing (SS) below the thermal limit of 60mV/dec. SS as low as 15mV/dec and VTH close to 0.15V have been achieved in simulations. Experimentally, some TFETs have also exhibited < 60mV/dec albeit at very low currents levels (~pA range). However, the subthreshold swing has been found to degrade rapidly with rise in current level to render this effect to no advantage. Another factor affecting experimental TFETs, particularly Si-based TFETs, is on-current levels several magnitudes lower in comparison to conventional MOSFETs. Moreover TFETs, which operate fundamentally as gated pin reverse biased diodes, suffer from ambipolar behavior.

In this study, Silicon Source Pocket Tunnel FET was studied and fabricated using dopant engineering to create a pocket near the source junction. The pocket near the source junction helps to achieve higher performance than comparable pin TFET structures. The device concept and simulation results will be presented. Device fabrication, experimental results (showing the effect of pocket doping and annealing schemes on device behavior) and device merits and issues will be discussed.

Biography:
Venkatagirish Nagavarapu received the B.Tech. degree in Electrical Engineering from the Indian Institute of Technology, Bombay, India, in 2001 and M.S. Degree in Electrical Engineering (Physical & Wave Electronics) from University of California, Los Angeles (UCLA) in 2008. He is currently a Ph.D. candidate with Prof. Jason Woo in the Department of Electrical Engineering, University of California, Los Angeles. His research interests include novel asymmetric device structures and transistor design for high performance to meet scaling challenges.