Personal tools
Home Events Events Archive 2010 The Design of Flash ADCs with Large Offsets using Redundant Comparators

The Design of Flash ADCs with Large Offsets using Redundant Comparators

— filed under:

  • PhD Defenses
When Sep 28, 2010
from 03:00 PM to 05:00 PM
Where Engr IV Room 57-124
Add event to calendar vCal

Victoria Wang
Advisor: Dejan Markovic

Tuesday, September 28, 2010 at 3:00pm
Engr IV Room 57-124

Amid concerns over the increasing effects of process variability, the march towards smaller devices forges on. Analog designers have advanced with the technology by developing circuit techniques to adapt to these manufacturing limitations. Unfortunately, these techniques can result in increased power and complexity and are not necessarily robust to voltage and dimension scaling. These problems, coupled with a host of new low-power and/or high-speed application drivers in the bio-medical and communication fields have spawned a new approach to designing robust analog blocks. Rather than remove the variations, calibration techniques have been developed to use redundancy to tolerate the effects of process variability. Redundancy is currently in use as a technique for combating digital defects and has proved quite successful. The application of it to analog blocks is a promising way to obtain desired circuit performance while still reaping the benefits of the scaled technology. Of particular interest to us is the flash analog-to-digital converter because its simple structure makes it an ideal candidate for exploring alternate design methods. Our goals for this thesis were two-fold:

1. The first question we address is how to estimate the comparator-offset variations? Although a multitude of models exist for modeling transistor variations, there is a large disconnect between the models and circuit design. In most cases, the developed models are complicated to fit or time consuming. Using measured data we developed a compact model for random process variability that provides insight into the sources of variability in a design. The model will then be applied to comparator offset voltage estimation.

2. Our second question is how can a Flash ADC be designed to tolerate the variability? We explore the idea of using a highly redundant digital approach that allows many less accurate blocks to replace a single accurate block. By turning the problem into a graph we can solve for maximum ENOB.

Tyan-Lin Wang received his B.S. and M.S. degrees in Electrical Engineering from UCLA in 2002 and 2004, respectively. He is currently a Ph.D. candidate in the Electrical Engineering department at UCLA.

Document Actions