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Home Events Events Archive 2010 Vertical Multiple-Stack Transistors for Ultra-High-Density Nonvolatile Memory Device

Vertical Multiple-Stack Transistors for Ultra-High-Density Nonvolatile Memory Device

— filed under:

  • PhD Defenses
When Sep 27, 2010
from 01:00 PM to 02:00 PM
Where Engr IV Faraday Room 67-124
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Ji Young Kim
Advisor: Kang L. Wang

Monday, September 27, 2010 at 1:00pm
Engr IV Faraday Room 67-124

High density data storage is critical for today's explosive growth in memory intensive applications. To meet such demands, various emerging devices have been extensively explored including three-dimensional (3D) devices based on CMOS technology, which is by far the most promising candidate for realizing the ultra-high-density storage in the near future. However, there is no 3D chip architecture integrating logic circuits and the 3D memory device to date, which can significantly increase the storage capability beyond physical scaling limits. In this study, novel 3D memory chip architecture of Stacked-Memory-devices-On-Logic (SMOL) has been developed achieving up to 95% of cell-area efficiency by directly building up memory devices on top of front-end CMOS devices. In order to realize the SMOL, a unique 3D Flash memory device and vertical integration structure have been successfully developed. The SMOL architecture has great potential to achieve tera-bit level memory density by stacking memory devices vertically and maximizing cell-area efficiency. Furthermore, various emerging devices can replace the 3D memory device to develop new 3D chip architectures.

Ji Young Kim received B.A. in Physics from Hanyang University, Korea in 1995 and M.S. in Electronic and Electrical Engineering from Pohang University of Science and Technology (POSTECH), Korea in 1997. He joined semiconductor division of Samsung electronics in 1997. From 2005, he joined the DRL group of UCLA for his Ph. D. research.

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