Vertical Tunneling Transistors for Continued Voltage Scaling

Ahmet Tura
Advisor: Jason Woo

Tuesday, May 25, 2010 at 2:00pm
Engr. IV Maxwell Room 57-124

Abstract:
In the last few decades, MOSFET scaling has enabled smaller and faster transistors that consume less power per operation. But as device dimensions were shrunk into the sub-65nm regime, non-scalability of the subthreshold swing to below 60mV/decade has resulted in significant increase in OFF state current and stand-by power dissipation. Achieving the required ION/IOFF ratio without an increase in IOFF is greatly needed to further scale VDD and reduce circuit delay and power consumption simultaneously. Impact Ionization FET, Feedback FET, Nano-Electro-Mechanical FET, p-i-n and p-n-p-n Tunnel FETs were proposed as novel device concepts that achieve sharper swings than 60mV/decade. In this work, a detailed comparison of these steep subthreshold devices in terms of speed and power is presented and the challenges for each device to become a viable MOSFET alternative are outlined. P-n-p-n tunnel FET is identified as one of the more promising steep subthreshold devices. Very sharp optimized dopant profiles are obtained for p-i-n and p-n-p-n tunnel FETs with molecular beam epitaxy (MBE) and devices are fabricated with a low thermal budget vertical process flow. It has been found that the p-n-p-n tunnel FET has improved subthreshold swing, ION and tunneling resistance over a p-i-n tunnel FET.

Biography:
Ahmet Tura received his B.S. with honors in Electrical Engineering from California Institute of Technology in 2003. He was a part of Caltech Asynchronous VLSI Research Group and Caltech MEMS Research Group during his undergraduate years. Then he joined the UCLA CMOS Lab to work towards his Ph.D. degree. At UCLA, he has worked on MOSFET structures to improve subthreshold characteristics beyond the classical limit of 60mV/decade that would enable circuit operation at Vdd=0.5V or below.