VLSI Implementation of a Low Power, High Energy Efficient, Quasi-ML Fixed Complexity Sphere Decoder for MIMO Communication Systems

Kelvin Lee
Advisor: Babak Daneshrad

Tuesday, April 27, 2010 at 11:00am
Engr. IV Maxwell Room 57-124

Abstract:
In this talk, a novel MIMO sphere decoding algorithm with power-aware architecture and circuit techniques will be presented.

Multiple-Input Multiple-Output (MIMO) technology plays a revolutionary role in the development of 3G-LTE and 4G wireless communication systems. Applying multiple antennas at both the transmitter and receiver sides, the spectral efficiency can be significantly improved without sacrificing extra bandwidth. The exhaustive-search maximum likelihood (ML) algorithm is the optimal MIMO detection method. However, its complexity increases exponentially as constellation size or antenna array increases. To address this issue, sphere decoder (SD) has been proposed as an alternative approach to achieve ML bit error rate (BER) with dramatically reduced complexity. Meanwhile, to meet the stringent battery capacity constraint, SD hardware realization must be optimized at all design aspects to ensure a low power, high energy efficient VLSI implementation.

To evaluate its effectiveness in energy efficiency, the proposed sphere decoder is implemented in IBM low-VT, 90 nm, 8 metal layer standard CMOS technology. It supports 4 x 4 antenna array with flexible modulation from BPSK to 16-QAM. At 0.8V and 125oC, the estimated peak throughput exceeds 1.44Gbps with the core area of 1.3 mm2. At room temperature and 0.8V core voltage supply, the measured power is 4.692 mW with 400 Mbps constant throughput. This VLSI realization achieves 11.73 pJ/bit which shows a 61% improvement in energy efficiency over the other state-of-the-art sphere decoders recently reported in the literature.

Biography:
Kelvin Lee received his BS degree in Physics from Taiwan Fu-Jen University in 1988 and the MS degree in Electrical Engineering from University of Southern California in 1991, respectively. From 1992 to 2002, he worked for Western Digital Corp., VLSI Technology Inc. and Broadcom Corp. as design engineer and project lead for various commercial products. Since 2003, he joined University of California, Los Angeles (UCLA) to pursue the Ph.D. degree in the Electrical Engineering department. His research interests include MIMO communications, high-speed, low-power VLSI implementation and digital signal processing architecture.