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A 2.8 to 3.2 GHz fractional-N digital PLL with ADC-assisted TDC and Inductively-Coupled Fine-Tuning DCO

— filed under:

  • PhD Defenses
When Mar 21, 2012
from 02:00 PM to 04:00 PM
Where ENGR. IV Bldg. Maxwell Room 57-124
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Chih-Wei Yao

Advisor: Alan N. Willson, Jr.



A 2.8 to 3.2 GHz fractional-N digital PLL implemented in 0.18 um CMOS is presented. The PLL architecture has the form of a classic delta-sigma fractional-N PLL. A PFD generates “up” and “down” pulses from the reference and divided-down DCO clock. The TDC converts the width of “up” pulse to digital words. The quantization noise introduced by a third-order sigma-delta modulator through the multi-modulus divider is cancelled out at TDC output.  A digital loop-filter further processes the TDC output to drive the DCO. A divider with two-stage retiming improves linearity to reduce fractional spurs without increasing the in-band noise floor. A resistively interpolated ADC is employed to boost TDC resolution by five times to achieve 2 ps effective resolution. A dither-less DCO with an inductively coupled fine-tune varactor bank improves tuning step-size by 16.6x to 20 kHz without adding large a parasitic capacitance that would compromise the achievable tuning range. The techniques introduced can be applied to more advanced CMOS process technology to yield better performance and lower power consumption.

With a 52 MHz reference clock and a loop-bandwidth of 950 kHz, the prototype achieves 230 fs rms jitter integrated from 1 kHz to 40 MHz offset while drawing 17 mW from a 1.8V supply. The phase noise floor is -111.6 dBc/Hz at 500 kHz offset. The reference spur is -75 dBc and the worst case fractional-N spur is -55 dBc. A FOM of -240.4 dB is achieved, and this design occupies core area of 0.62 mm2.



Chih-Wei Yao received the B.S. degree in Electrical Engineering from UCSB in 1994.  From 1996 to 2000, he was a digital integrated circuit design engineer in Sun Microsystems. From 2000 to 2002, he is a mixed-signal design engineer in Silicon Bridge. He received M.S. degree in Electrical Engineering from UCLA in 2004. Since 2008, he is a RFIC design engineer in Marvell Semiconductor.  He is currently pursuing his Ph.D. in UCLA. His research activities are presently in the area of high performance frequency synthesizers.

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