A 25-Gb/s 5-mW CMOS CDR/Deserializer
Aug 28, 2012
from 11:00 AM to 12:30 PM
|Where||ENGR. IV Bldg. Faraday Room 67-124|
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Jun Won Jung
Advisor: Behzad Razavi
Recent studies indicate that the input/output (I/O) bandwidth of serial links must increase by 2 to 3 times every two years so as to keep up with the demand for higher data rates. In order to manage such bandwidths with reasonable power consumption, an efficiency of around 1 mW/Gb/s for the overall transceiver is targetted, necessitating a much smaller value for each building block.
The latches, demultiplexers, and frequency dividers comprising a broadband receiver consume the lion’s share of the power. Current-steering circuits run at high speed but draw considerable static power whereas rail-to-rail CMOS circuits can avoid static bias but at the cost of speed.
This work describes the development of a 25-Gb/s clock and data recovery (CDR) circuit and a deserializer that, through the use of “charge steering” and other innovations, achieve a twenty-fold reduction in the power dissipation with respect to the prior art. Realized in 65-nm CMOS technology, an experimental prototype draws 5-mW from a 1-V supply, exhibiting an integrated clock jitter of 1.52 ps,rms and a jitter tolerance of 0.5 unit interval at a jitter frequency of 5 MHz.
Jun Won Jung received his B.Sc. in Electrical Engineering from Seoul National University in 2004, and his M.Sc. in Electrical Engineering from the University of California, Los Angeles in 2008. He is currently pursuing the Ph.D. degree at UCLA. His research interests include high-speed wireline transceivers.