A Compact, Low-Power 7-bit 2.2-GS/s ADC for Ultra High-Speed Digital Communications
Nov 18, 2011
from 10:00 AM to 11:00 AM
|Where||Maxwell Room, 57-124 Engr. IV|
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Advisor: Prof. M-C. Frank Chang
A 7-bit 2.2GS/s Nyquist-rate analog-to-digital converter (ADC) for low-power gigabit wireless
communication system is presented in this work. The required sampling rate is achieved by time-
interleaving four power-efficient subranging ADCs. To mitigate the effect of channel mismatches in the time-interleaving ADC, offset calibration and distributed resistor array reference are implemented. With offline DC offset calibration through binary-weighted corrective current sources, channel offset mismatch converges to zero with negligible power in normal operation. By employing distributed resistor array as the ADC’s reference voltage buffer, channel gain mismatch is alleviated through better matching poly resistors. To reduce the number of interleaved channels so as the total chip area, a time-splitting subranging ADC architecture is proposed. With a larger timing window for amplification phase and encoding phase, the proposed time-splitting subranging architecture achieves a much higher sampling rate over conventional subranging architecture while maintain low power consumption. The prototype is implemented in 65nmn CMOS, occupying only 0.3mm2 active area and consumes 40mW at 2.2GS/s from a 1V supply. Measured SNDR (signal-to-noise ratio) and SFDR (spurious-free dynamic range) are 38dB and 46dB, respectively, with a 1.08GHz input at 2.2GS/s sampling rate. The equivalent ENOB (effective number of bits) is 6.0 bits and the ADC achieves a figure-of-merit (F.O.M.) of 0.28pJ/conv.-step.
I-Ning Ku received the B.S. degree in electrophysics from National Chiao-Tung University, Hsin-Chu,
Taiwan, R.O.C., in 1999, and the M.S. degree in electrical engineering from University of California,
Los Angeles in 2001. He is currently pursuing the Ph.D. degree in electrical engineering at University of California, Los Angeles. His research interests are high-speed ADC/DAC design and high-precision mixed-signal design.