A System-Level Analysis of a Wireless Low-Power Biosignal Recording Device
Mar 21, 2012
from 04:00 PM to 06:00 PM
|Where||ENGR. IV Bldg., Maxwell Rm. 57-124|
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Rodney J. Chandler
Advisor: Jack W. Judy
Development of brain-machine interfaces and treatment of neurological diseases can benefit from analysis of recorded data from implanted electrodes. Existing wireless neural recording systems are often bulky, dissipate too much heat to be implanted, or only have a small number of channels.
A system-level analysis of wireless recording circuitry that overcomes these deficiencies is described in this work. The overall system comprises of an analog front end (AFE), digital signal processing (DSP), and transmitter (TX). Each of these blocks is analyzed, and system-level specifications are derived. Based on these specs, each block can be optimized for low power and small area. The analog front-end uses open-loop amplifiers to support lower voltage operation than previously published work. The optimization of this 1 V amplifier provides similar performance to other 3 V amplifiers. Literature reviews of digital-signal processors and transmitters are used to construct approximate models of power versus performance. These models are then used to investigate the overall system power with different levels of digital processing.
With a target application of neural spike recording, four modes (raw data, spike detection, feature extraction, and clustering) were analyzed. A system that uses feature extraction yields the lowest overall power, supports 400 channels with a practical wireless link, and consumes approximately 8 mW. When compared to other published work, the proposed system is 50 % lower when configured for 100 channels.
A prototype amplifier was also fabricated to measure performance in a 65-nm CMOS process that is needed for low-power digital signal processing. The amplifier performance was comparable to other recently published amplifiers with 2.5 uV noise in 10 kHz bandwidth while dissipating 17.2 uV from a 1 V supply. Programmable bias currents in the amplifier, to exploit the trade-off between noise and power, were proposed to set each amplifier's noise level (and power) to meet requirements for accurate spike detection. In a system with a large number of channels with different signal and noise conditions, setting each amplifier current to meet a required SNR based on feedback from the DSP can save significant power. A use case with spike 3-sigma amplitudes covering 50 to 500 uV shows a power dissipation of 38 % compared to a constant biasing scheme.