Circuit and Interconnect Modeling and Optimization for 3D IC and High Bit-Rate Applications
Aug 02, 2012
from 01:00 PM to 03:00 PM
|Where||ENGR. IV Bldg., Tesla Room 53-125|
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Advisor: Professor Lei He
The advance of modern integrated circuit (IC) processes has supported increasing date rates on chip-to-chip communications in many consumer and professional applications, such as multimedia and optical networking. Serial links have successfully evolved and achieved the bit-rate of several tens of Gb/s per channel by applying new generations of IC process and advanced circuit techniques. However, as process technologies further scale down, severe process variations significantly impact the performance of high bit-rate serial links and makes today’s circuit designs have to be optimized not only for nominal performance but also for a reasonable yield. On the other hand, three-dimensional (3D) IC provides a smaller form factor, higher performance, and lower power consumption than conventional 2D integration by stacking multiple dies vertically. Through-silicon-via (TSV) enables the vertical connectivity between stacked dies or interposer and is a key technology for 3D IC. However, electrical signaling over TSVs presents a unique set of design challenges and thus requires accurate modeling and detailed signal and power integrity analysis.
In this research, the bottlenecks in through-silicon-via (TSV) modeling, variation-aware circuit optimization and efficient performance evaluation for high bit-rate applications are analyzed, and solutions are presented. A simple yet accurate pair-based model for multi-port TSV networks (e.g., coupled TSV array) is proposed by decomposing the network into a number of TSV pairs and then applying circuit models for each TSV pair. This methodology is first verified against full-wave electromagnetic (EM) simulation for up to 20GHz and subsequently employed for a variety of examples of signal and power integrity analysis. A rigorous frequency-dependent circuit model for horizontal coplanar waveguide (CPW) on silicon interposer is also derived based on partial equivalent element circuit (PEEC) in layered metal-isolator-semiconductor (MIS) media. For high bit-rate serial links, an optimization framework is proposed for the joint design time and post-silicon tuning optimization for digitally tuned analog circuits, and can be used to maximize the yield in serial link transmitter design and the phase-locked-loop (PLL) design subject to the area and power constraints. Moreover, an efficient mathematical method is proposed to capture the worst-case data-dependent jitter and noise without lengthy simulations. These modeling and optimization methodologies can be applied to accurately explore the chip-to-chip integration and signaling schemes at early design stage in today's and tomorrow's 3D IC and high bit-rate circuit design.
Wei Yao received his B.S. and M.S. degree in Electrical Engineering from National Taiwan University, Taipei, Taiwan, in 2002 and 2004, respectively. He is currently working toward his Ph.D. degree in the Electrical Engineering Department at UCLA. His research interests include on-chip and chip-to-chip power integrity, signal integrity, and ASIC circuit design optimization.