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Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies

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What
  • PhD Defenses
When Sep 12, 2012
from 02:00 PM to 03:30 PM
Where ENGR. IV Bldg. Maxwell Room 57-124
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Rani Abou Ghaida

Advisor: Professor Puneet Gupta

 

Abstract

The semiconductor industry is undergoing several radical changes in manufacturing, device and interconnect technologies and is likely to continue to do so in the future. These changes will also drive and interact with increasing variety in circuit objectives and layout styles. The result is an increasing demand and pressure on design enablement to ensure technology profitability and timely adoption. Moreover, for the scaling to every new node, a large number of technological choices are presented and early technology assessment, before the actual development of technologies, has become more necessary than ever as a means to ensure faster adoption and manageable technology/design flow development costs. Technology assessment is currently a highly unsystematic procedure that relies on small-scale experiments, fabrication tests, and much on speculations based on technologists/designers experience with previous technology generations. In the first part of my defense, I present our work on design enablement of patterning technologies, namely double/multiple-patterning lithography. In the second part, I describe DRE, a computation infrastructure we proposed for systematic and early design rule evaluation and design-centric assessment of technologies. This infrastructure can be used to co-evaluate and optimize design rules, patterning technologies, layout methodologies, and library architectures at early stages of technology development before significant investment in R&D and design enablement had been made.

 

Biography

Rani S. Ghaida is a fourth-year PhD candidate at the department of Electrical Engineering at UCLA.  He earned the B.S. degree from the Lebanese American University in 2006 and the Master's degree from the University of New Mexico in 2008, both in Computer Engineering. In 2010, Rani was on internship at IBM Austin Research Lab, where he worked on the design enablement of multiple-patterning technology. In 2011, Rani was with IBM T. J. Watson Research Center where he worked on developing a platform for exploring design rules and patterning strategies for the 14nm node. His research work has been focused on Design/Technology Co-Optimization and Design for Manufacturability. He has 16 journal and conference publications and five pending patents in his field. Rani is a student member of UC Discovery IMPACT research center and the Semiconductor Research Corporation (SRC).

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