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Design of CMOS SOI for RF Switch Application

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What
  • PhD Defenses
When Nov 18, 2011
from 12:00 PM to 01:00 PM
Where Elliott Room, ENGR IV 53-135
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Ali Sajjadi
Advisor: Jason C.S. Woo

Abstract
The extensive growth of market for low-cost low-power wireless systems has encouraged widespread research on RF CMOS integrated circuits. While it is desirable to integrate the whole wireless system on a chip, there are parts of transceiver still challenging to integrate into the system. RF switch is one of those blocks and is traditionally implemented using GaAs technology. Until recently, CMOS switches could not fulfill the requirements of RF switch in a transceiver. However, continuous scaling of CMOS made it possible to reach CMOS switches comparable to their GaAs counterparts. These CMOS switches also have the benefits of low switching time, low and positive power supply, and single-ended control. In the previous studies, some methods have been introduced to overcome the challenges of designing CMOS RF switches, which mainly come from low mobility, low substrate resistivity, and small band-gap of silicon. SOI CMOS can overcome some of these challenges since, compared to Bulk CMOS, it has smaller capacitances, higher channel mobility, and better substrate isolation.

While intensive studies have been done on CMOS RF switches at the circuit level, very little effort has been put on studying the device for this specific application. In this work, RF switches are studied from the device perspective.

Effects of various device parameters including doping, thicknesses and overlaps on switch performance are discussed and some methods for improving the efficiency of circuit design techniques are introduced. Proper device design is shown to have huge impact on switch performance specifically for sub-100nm devices. Standard processes are compared for their suitability for switch design. It is shown that correct choice of devices in a standard process and proper design of the process are essential for achieving high performance switches in sub-100nm technology nodes.

Biography
Ali Sajjadi is a Ph.D. candidate in the Electrical Engineering department at UCLA. He received the B.Sc.degree in Electrical Engineering from Sharif University of Technology, Tehran, Iran in 2005 and the M.S.degree in Electrical Engineering from UCLA in 2007. He has been an intern in Broadcom Corp. cellular R&D group since March 2011. The primary focus of his research is design of CMOS RF switches.

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