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Home Events Events Archive 2012 Digitally Enhanced Wireless Transceivers for Multi-mode Reconfigurable Radios

Digitally Enhanced Wireless Transceivers for Multi-mode Reconfigurable Radios

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  • PhD Defenses
When Aug 28, 2012
from 02:00 PM to 03:30 PM
Where ENGR. IV Bldg. Elliott Room 53-135
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Rashmi Nanda

Advisor: Dejan Marković



Digitally enhanced wireless transceivers are gaining prominence due to their promise of greater integration, flexibility to adapt to varying SNR conditions, performance, and area benefit that comes with CMOS feature size reduction. These architectures rely on high-speed A/D and D/A conversion close to the antenna to maximize the extent of digital signal processing in the radio chain. A programmable digital front-end enables a wide range of tuning parameters to control the RF carrier, signal bandwidth, and baseband modulation scheme.

This work discusses the design of a digitally intensive linear transmit modulator that consists of a high-speed digital front-end followed by a ΣΔ modulator and a current-steering RFDAC. The digital front-end can be tuned for user-specified interpolation, filtering, and signal amplitudes. The ΣΔ modulator assists in reducing the resolution of the RFDAC. A new design approach that optimizes the noise-transfer-function of the ΣΔ modulator to minimize the power consumption in the digital core is presented.

The design of a corresponding digital front-end for radio receivers is also discussed. Prototype architectures for the radio transmitter and receiver digital front-end implemented in 65nm CMOS are presented.



Rashmi Nanda received her B.Tech. degree in Electronics and Electrical Communication Engineering from the Indian Institute of Technology, Kharagpur, India in 2006 and the M.S. degree in Electrical Engineering from the University of California, Los Angeles in 2008 respectively. She is currently a Ph.D. candidate at UCLA, working on digitally enhanced architectures for future radio systems.  She is interested in the optimization of DSP algorithms and architectures for high-speed and power-limited systems.

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