Implications of Modern Semiconductor Technologies in Gate Sizing
May 30, 2012
from 05:00 PM to 06:30 PM
|Where||ENGR. IV Bldg. Tesla Room 53-135|
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Advisor: Puneet Gupta
Gate sizing is one of the most flexible and powerful methods available for the timing and power optimization of digital circuits. As such, it has been a very well-studied topic over the past few decades. However, developments in modern semiconductor technologies have changed the context in which gate sizing is performed. The focus has shifted from custom design methods to standard cell designs, which has been an enabler in the design of modern, large-scale designs. We start by providing benchmarking efforts to show where the state-of-the-art is in standard-cell based gate sizing. Next, we develop a framework to assess the impact of the limited precision and range available in the standard-cell library on the power-delay tradeoffs.
In addition, shrinking dimensions and decreased manufacturing process control has led to variations in the performance and power of the resulting designs. We provide methods for gate sizing with statistical delay, and compute bounds to show that full statistical power optimization is not essential. Lastly, to address the complexities of doing in design in a yet immature process, we provide a method to perform incremental discrete gate sizing to account for both anticipated and unanticipated changes in the manufacturing process parameters.
John Lee is a PhD Candidate in the Electrical Engineering Department at UCLA. He received his BS and BA degrees from UC Berkeley and his MS degree from UCLA. His research interests are in the intersection of Applied Mathematics and Electrical Engineering, specifically in the applications of mathematical programming and optimization in the physical design of digital circuits.