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Home Events Events Archive 2012 Neural Spike Sorting in Hardware: From Theory to Practice

Neural Spike Sorting in Hardware: From Theory to Practice

— filed under:

  • PhD Defenses
When May 25, 2012
from 01:00 PM to 02:30 PM
Where ENGR. IV Bldg. Maxwell Room 57-124
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Sarah Gibson

Advisor: Dejan Marković




Most systems for electrophysiology are wired, and data is typically recorded onto hard disks for offline processing in software. But brain-machine interfaces, as well as many new research paradigms, require real-time, wireless acquisition systems. Wireless transmission of raw data is impossible for high-channel-count systems given the power constraints. Data rates could be reduced, thereby enabling wireless data transmission, by performing spike sorting—mapping each recorded action potential to the neuron that generated it—on a DSP at the recording site and transmitting only the sorting results. Our first objective was to design such a DSP. We first developed a standardized dataset and methodology in order to perform an extensive, unbiased comparison of published spike-sorting algorithms to determine which would be most appropriate for hardware implementation. We then considered various implementation issues, such as whether analog or digital spike detection is more efficient and how best to quantize neural signals. This work led to two low-power digital spike-sorting chips. Our second objective was to provide an offline solution for accelerating the processing of data that has already been recorded using conventional data-acquisition systems. Here, we present an FPGA-based spike-sorting platform that can reduce the time required to sort data from long experiments from several hours to just a few minutes. We attempted to preserve the flexibility of software by implementing several different algorithms in the design, and by providing user control over parameters such as spike detection thresholds.


Sarah Gibson received a B.S. in Electrical & Computer Engineering from Baylor University in 2005. She worked as a Mars Flight Project Intern at the Jet Propulsion Laboratory in 2006, and then as an intern on the James Webb Space Telescope at Northrop Grumman in 2007. In 2008, Sarah received an M.S. in Electrical Engineering from UCLA. She is currently a Ph.D. candidate at UCLA. Her research interests are in signal processing for neural systems and computational neuroscience.

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