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Analysis and Design of High-Speed ADCs

— filed under:

  • PhD Defenses
When Nov 28, 2012
from 04:00 PM to 06:00 PM
Where 57-124 Engr IV
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High-speed analog-to-digital converters (ADCs) are at the heart of many applications such as digital communication, video, and instrumentation. However, the power efficiency of ADCs tends to degrade as higher speeds and/or resolutions are sought. In this research, we introduce a low-power high-speed pipelined ADC architecture that employs a precharged resistor-ladder digital-to-analog converter (RDAC) and a multi-bit front end with a low-gain op amp. Avoiding the need for op amp nonlinearity calibration, the ADC only computes the gain error and corrects it in digital domain. In addition, RDAC simplifies the calibration logic and enables high-speed gain error calibration, thus correcting for the incomplete settling of the MDACs. Using simple differential pairs with a gain of 5 as op amps and realized in 65-nm CMOS technology, the 10-bit ADC consumes 36 mW at a sampling rate of 1 GHz and exhibits an FOM of 70 fJ/conv.-step.

A critical issue in the design of high-speed ADCs relates to the errors that result from comparator metastability. Studied for only flash architectures, this phenomenon assumes new dimensions in pipelined converters, creating far more complex error mechanisms.  In this dissertation, we present a comprehensive analysis of comparator metastability effects in pipelined ADCs and develop a method to precisely predict the error behavior for a given input signal p.d.f.



Sedigheh Hashemi received her B.Sc. and M.Sc. degrees in Electrical Engineering from the University of Tehran, Iran, in 2005 and 2007, respectively. In fall 2008, she joined the PhD program of UCLA, where she has been conducting research at the CCL lab of EE department. Her research focus is on the design of high-speed data converters.

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