Digitally-Calibrated Reconfigurable Analog-to-Digital Converters
Feb 25, 2013
from 11:00 AM to 01:00 PM
|Where||Engr. IV Bldg., Faraday Room 67-124|
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Advisor: Chih-Kong Ken Yang
Modern digital communication systems target satisfying multiple standards. Applications include read channels of data storage systems, PCIe links, FPGA I/Os, and multi-standard radios. This stimulates the research on reconfigurable analog-to-digital converters (ADCs) to serve as a key building block at the front-end of such systems. Conventional reconfigurable designs suffer from poor figure-of-merit (FoM) scaling with different resolutions, which reduces their flexibility. The limited efficiency of these techniques is attributed to the fact that they fix the ADC architecture for all configurations, whereas the optimum architecture depends on the target resolution.
This dissertation introduces an architecture reconfigurable ADC that efficiently covers a wide range of resolutions by configuring the ADC to the proper architecture for each resolution. This leads to a reconfigurable ADC nearly as efficient as dedicated designs in both area and power. The dissertation also investigates the efficiency of using body voltage trimming calibration for data converters. The tradeoffs of this technique are studied in details. Suggested methods are presented to extend the use of bulk voltage trimming beyond technology limitations with minimal area and power overhead and no special technology requirements.
Two prototype chips are implemented in 65-nm CMOS to verify the results of this study. The first chip is a 2.5-10GS/s reconfigurable flash ADC. The ADC can be configured to work as a 3-bit, a 4-bit, or a 5-bit ADC an FoM of 0.46pJ/conv-step. The second chip is a 1.5-4GS/s “architecture” reconfigurable ADC. The ADC covers resolution range from 3b to 7b, and achieves an FoM of 0.46pJ/conv-step at 7b.
Ramy Awad received the B.Sc. and M.Sc. degrees both in electrical engineering from Ain-Shams University, Cairo, Egypt, in 2003 and 2007, respectively. Since 2008, he has been with the University of California, Los Angeles, where he is currently working toward the Ph.D. degree in integrated circuits and systems under supervision of Professor C.-K. Ken Yang. His research interests include high-speed mixed-signal and high-speed data converters.