Emerging Device Technology for Future Computing Paradigms
Apr 05, 2013
from 11:00 AM to 12:30 PM
|Where||Engr. IV Bldg., Shannon Room 54-134|
|Contact Name||Prof. Jason Woo|
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As the CMOS scaling will soon approach its physical limit, it is necessary to think about new computing paradigms that continue improving the system performance. We are entering the “Big Data” era which puts data at the center of computing. The size of data sets is rapidly exceeding exascale. Therefore, increasing the data bandwidth of the memory sub-system is demanding. Emerging memory technologies such as oxide based resistive random access memory (RRAM) may bring enormous opportunities for evolution or revolution of today’s computing system architecture.
In the first part of the talk, I will discuss the physical mechanism of resistive switching phenomenon in oxides. To elucidate the oxide RRAM device physics, various characterization techniques were employed to identify the electron conduction mechanism and oxygen ion migration dynamics. Then a Kinetic Monte Carlo numerical simulator was developed for understanding the variability of resistive switching. Finally a compact device model was developed for circuit/system-level simulations.
In the second part of the talk, I will explore the potential applications of oxide RRAM technology, including 1) cost-effective 3D integration of RRAM cross-point array as NAND FLASH replacement; 2) non-volatile reconfigurable memory for FPGA application; 3) artificial synaptic device for implementing adaptive learning algorithms in bio-inspired neuromorphic computing system.
The directions of my future research are to first change today’s memory system hierarchy, then bring non-volatility and programmability into the logic, and eventually break the Von Neumann bottleneck between the computation and storage. To accomplish these goals, my future research calls for an active interaction between fundamental physics exploration, material/device engineering, and peripheral circuitry and system architecture co-design.
Shimeng Yu received the B.S. degree in microelectronics from Peking University in 2009, and the M.S. degree in electrical engineering from Stanford University in 2011, where he is expected to obtain the Ph.D. degree in summer 2013. He did summer internship in IMEC, Belgium in 2011, and IBM TJ Watson Research Center in 2012, respectively. His research interests are the fundamental physics exploration of the emerging device technologies and their applications for future computing paradigms, such as 3D memory integration, embedded memory, logic-in-memory, reconfigurable computing, bio-inspired neuromorphic computing, etc. He has been working on the fabrication, characterization, and modeling of oxide resistive random access memory (RRAM) since 2008. He has authored or co-authored one book chapter, >50 journal and conference papers with a total citation > 350 and H-index 11.