From Deep Trenches to Skyscrapers - Orthogonal Scaling
Jan 28, 2013
from 01:00 PM to 02:00 PM
|Where||Engr. IV Bldg., Shannon Room 54-134|
|Contact Name||Prof. Abeer Alwan|
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IBM Systems & Technology Group
The absence of cost effective lithography and patterning schemes is predicted to make the historical expectations of the cost –performance benefits of scaling (popularly known as Moore’s Law) difficult to sustain. In this talk we introduce the concept of orthogonal scaling. Orthogonal scaling refers to features that can be added to the technology which significantly enhance the technology and which are sustainable over several generations of technology. We will examine three such orthogonal features that have either been implemented or being actively worked on. The first is embedded memory, where the integration of logic based embedded DRAMs can effectively yield up to a generational jump in effective density. The second case we consider is the use of deep trench decoupling that can reduce mid-frequency power supply noise in processor and general purpose ASICs effectively adding up to10% in chip performance above the scaling entitlement and finally, three dimensional integration which depending on its implementation can address die size, performance, process simplicity and cost beyond the expectation of semiconductor scaling. We summarize this talk with where the fundamental limits are and what our long-term options are for the evolution of a systems’ based scaling methodology.
Subramanian S. Iyer is an IBM Fellow at the Systems & Technology Group, and is responsible for technology strategy and competitiveness, embedded memory and Three-Dimensional Integration.He obtained his B.Tech in Electrical Engineering at the Indian Institute of Technology, Bombay, and his M.S. and Ph.D. in Electrical Engineering at the University of California at Los Angeles. He joined the IBM T. J. Watson Research Center in 1981 and was manager of the Exploratory Structures and Devices Group till 1994, when he co-founded SiBond LLC to develop and manufacture Silicon-on-insulator materials. He has been with the IBM Microelectronics Division since 1997. Dr. Iyer has received two Corporate awards and four Outstanding Technical Achievement awards at IBM for the development of the Titanium Salicide process, the fabrication of the first SiGe Heterojunction Bipolar Transistor, the development of embedded DRAM technology and the development of eFUSE technology. His current technical interests and work lie in the area of 3-dimensional integration for memory sub-systems and the semiconductor roadmap. He is a Master Inventor. He received the Distingushed Aluminus award from the Indian Institute of Technology, Bombay in 2004. Dr. Iyer has authored over 175 articles in technical journals and several book chapters and co-edited a book on bonded SOI. He has served as an Adjunct Professor of Electrical Engineering at Columbia University, NY. He was honored as the Asian Engineer of the Year in 2011. He is the recepient of the 2012 IEEE Daniel Nobel award for emerging techologies In his spare time, he studies Sanskrit and role of Indic languages, traditions and culture in different parts of the world.