In-situ SRAM Static and Dynamic Stability Estimation
Nov 20, 2012
from 12:00 PM to 02:00 PM
|Where||57-124 Engr IV|
|Contact Name||Henry Park|
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Scaling of the device size has been a key part of CMOS circuit design to maximize the transistor density and to reduce power consumption. With increasing process and parametric variations, large-scale integration of SRAM bit cells requires an accurate estimation of the failure conditions during read/write operation. Estimation of an aggregate metric such as yield can be possible primarily from simulations, yet on-die built-in self testing (BIST) circuit can provide more useful information on the cell stability to prevent such failure conditions for each die. However, previously published BIST techniques and their estimation results do not properly correlate to the existing stability models with low estimation accuracy (R2 < 0.6). This work proposes an on-die BIST circuitry for rapid estimation of static and dynamic stability of 6T SRAM cell during read/write operation with high estimation accuracy (R2 ≥ 0.8).
The first part of the talk describes a rapid stability estimation technique to predict the stability of SRAM cells within an array. Previously published stability metrics are reviewed, and one read and one write metric are chosen to gauge the likelihood of failure of a cell. Unlike previously published measurement approaches which require precise control on the supply levels and very long measurement times, the proposed approach estimates the stability metrics based on the cell read/write currents created by controlling the supply with a few discrete levels. A polynomial-based formula is presented to connect the measured read/write currents to the stability. A compromise between the number of supply controls and estimation accuracy is demonstrated.
The test circuit is implemented in a 65nm CMOS technology. The chip comprises of a DUT 32kb SRAM with current sensing circuits. The on-chip amplifier-based current sensing circuits uses a VCO-based ADC to translate the small cell currents (~10s uA) to digital values with 10-bit resolution and 1.25MS/s sampling speed. The accuracy of the proposed stability estimation model is verified with measurement data over more than 10 dies. After establishing the static stability prediction model, dynamic characteristic of the cell stability is investigated by correlating the measured dynamic stability to the estimated static stability.
Henry Park received the B.S.E.E. (summa cum laude) degree from Seoul National University, Seoul, Korea, in 2003, and the M.S.E.E. degree from UCLA, CA, in 2009. From 2003 to 2006, he was with Hunter Technology, Seoul, Korea, where he developed microprocessor embedded systems with digital and analog interface. During the summer and fall of 2009, he was with Broadcom, Irvine, CA, where he was involved in high precision data converters and noise chopper design. His research interests include data converters and statistical analysis of memory cell stability.