Logic Synthesis for FPGA Reliability
May 17, 2013
from 10:30 AM to 12:00 PM
|Where||Engr. IV Bldg. Tesla Rm. 53-125|
|Contact Name||Zhe Feng|
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Advisor: Lei He
Logic synthesis is one of the key stages in the computer-aided design (CAD) flow for a field programmable gate array (FPGA) based design. It usually consists of a series of optimization iterations to improve the quality of results (QoR) of the design. Besides the traditional objectives (e.g., performance, area, power), reliability is becoming a main concern as modern FPGAs have advanced to 20nm technology, due to reduction in core voltage, decrease in transistor geometry, and increase in switching speed. However, the existing techniques for the reliability enhancement of FPGA-based designs fall behind industrial needs in terms of cost (e.g., area and power overhead), CAD flow, runtime, and FPGA architecture.
To fill the gaps, this dissertation proposes several novel logic synthesis algorithms. The first algorithm is seeking for the formal method to improve the reliability of FPGA-based designs while incurring minimal area and power overhead. The algorithm formulates the problem of the reliability under random faults as a stochastic satisfiability (SSAT) based Boolean matching, and employs robust templates to rewrite the netlist, to maximize the stochastic yield rate. To ensure not breaking the current CAD flow, a logic synthesis algorithm is proposed in the dissertation which performs a SAT-based in-place reconfiguration in the look-up table (LUT) to masks soft errors, with no change of functionality and topology of the netlist. In addition, the dissertation proposes three fast in-place logic synthesis algorithms targeting the modern FPGA architecture including both LUTs and interconnects. The three algorithms perform simulation guided netlist analyses and utilize don’t cares in the netlist to enhance the reliability. The effectiveness of the proposed algorithms is verified by experimental results.
Zhe Feng received the B.S. degree in computer science from Northeastern University, Shenyang, China, in 2004, and the M.S. degree in computer science from Tsinghua University, Beijing, China, in 2007, respectively. He is currently pursuing the Ph.D. degree in the department of electrical engineering, University of California, Los Angeles (UCLA). He joined the Design Automation Laboratory led by Professor Lei He since 2007. His research interests are in computer-aided design algorithms for VLSIs, including logic synthesis algorithms, placement and routing algorithms, and the ESL design methodology.