Computational Assessment of Future Semiconductor Technologies
Feb 12, 2014
from 12:00 PM to 01:30 PM
|Where||Engr. IV Bldg., Tesla Room 53-125|
|Contact Name||Prof. Puneet Gupta|
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Dr. Rani Ghaida
Advisor: Prof. Puneet Gupta
Hosted by: Professor Mani Srivastava
Semiconductor technologists and circuit designers alike constantly find themselves in a dilemma of choice. For scaling to every new technology node, they must decide on an overwhelmingly large number of alternatives: fabrication technology, layout methodologies and constraints, circuit styles, interconnect stacks, standard-cell library schemes, and device architecture. Making informed technological decisions requires accurate projection of their design impact. The most crucial design-relevant quality metric for a technology is geometric constraints it imposes on layout, known as design rules. Rules complexity is increasing with miniaturization and, today, traditional rule evaluation is incapable of handling such complexity effectively.
Rethinking technology development, this talk presents a computational approach and an infrastructure for the systematic evaluation of design rules and technology choices. The infrastructure evaluates key design-quality metrics of area, manufacturability, variability, and delay in minutes – as opposed to weeks with traditional methods – without loss of accuracy (within 1% error in area). This speedup radically changes the way a technology is defined, allowing a wide range of rules and technological choices to be explored and, hence, unfolding new technology combinations that are more beneficial. Furthermore, the infrastructure only requires easy-to-extrapolate technology parameters, which allows its application at early stages of technology development before significant investment in R&D and design enablement had been made. Using the infrastructure, researchers across the spectrum of microelectronics – process/technology developers and circuit/system designers – will be able to redirect R&D efforts towards more viable technology options and avoid unforeseen disruptions of future technologies.
Dr. Rani Ghaida is a Principal Engineer at GlobalFoundries in the Design Enablement Division in Milpitas, CA. He has a PhD in Electrical Engineering from UCLA and a M.S. and B.S. in Computer Engineering from the University of New Mexico and Lebanese American University. During his PhD studies, Rani was on two internships at IBM Research, one at Austin Research Lab and another at T. J. Watson Research Center. His research work has been primarily focused on the development of computational techniques and mathematical models for exploring, defining, optimizing, and enabling semiconductor technologies in a digital design context. While a PhD student, his work had been used and acquired by some of the leading semiconductor companies spanning various industries: integrated device manufacturing, foundry, research, and electronic design automation.
Dr. Ghaida has published more than 20 technical papers in peer-reviewed conferences and refereed journals and has 4 granted US patents and 4 filed. He is the recipient of the 2012 Outstanding PhD Dissertation Award from the European Design and Automation Association (EDAA) and a number of other awards, most notably the IBM Invention Achievement Plateau Award and the SRC Inventor Recognition Award.