Data Centric Computing in Emerging Technologies: A PCM-CMOS Hardware Accelerator
Oct 28, 2013
from 01:00 PM to 02:30 PM
|Where||Engr. IV Bldg., Shannon Room 54-134|
|Contact Name||Professor Jason Woo|
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Dr. Jing Li
Research Staff Member at IBM
The confluence of disruptive technologies beyond CMOS and "Big Data" workloads calls for a fundamental paradigm shift from homogenous compute-centric system to new heterogeneous data-centric system for better innovation, competition and productivity. With the objective of rethinking data-centric system design from ground up, I will present a PCM-CMOS hardware accelerator based on the concept of ternary content addressable memory (TCAM) using emerging memory technology i.e., phase change memory (PCM). In particular, a fully-functional heterogeneous chip as designed and fabricated for the first time, achieving >10x cell area reduction compared to homogenous CMOS-based at the same technology node. The accelerator distributes compute units within storage elements in a cost-effective way, providing fine-grained control and high bandwidth close to data sources to avoid communication cost. It is particularly efficient in performing search operation with high and deterministic lookup rate. It can also be used as either a monolithic compute unit to perform direct data-flow computation or a monolithic storage media as storage class memory. Thus, it is an attractive solution for a wide range of data-intensive applications e.g., genome matching in bioinformatics, intrusion detection in cloud computing, etc. In spite of tremendous advantages in performance/cost/energy, design with heterogeneous PCM/CMOS technologies poses new challenges during hardware implementation due to the severely degraded operating margin introduced inherently by technology itself. To address these challenges, I will present two enabling techniques: 1) a clocked self-referenced sensing scheme and 2) a two-bit encoding. With these techniques, the fabricated chip can reliably operate at very low voltage (750mV). Finally, I will briefly present two critical techniques to move further into a more cost-effective design based on variable-bit storage.
Dr. Jing Li is a Research Staff Member at IBM T. J. Watson Research Center. Her general research interest is developing new computing paradigm driven by either technologies or workloads or both. Her primary area of interest is VLSI design-technology interaction with a strong emphasis on “design for transformation” (rather than "design for replacement"). She has received IBM Research Division Outstanding Technical Award in 2012 for successfully achieving CEO milestone, multiple invention achievement awards from IBM from 2010-present, IBM Ph.D. Fellowship Award in 2008, Meissner Fellowship in 2004 from Purdue University, etc. She has published more than 35 technical papers in referred journals and conferences and has more than 35 patents filed/issued. She won the Best Paper Award from IEEE Circuits and Systems Society VLSI Transactions for her contribution in STT RAM. She has been reviewers for numerous journals and conferences, and has been serving on the technical committee for DAC since 2011. She also represents IBM at premier industry conference IMW as a member of Scientific/Organizing Committee. Dr. Li received PHD degree from Purdue University in 2009 and BE degree from Shanghai Jiao Tong University in 2004.