Data Centric Computing in Emerging Technologies: A PCM-CMOS Hardware Accelerator
Feb 27, 2014
from 11:00 AM to 12:30 PM
|Where||Engr. IV Bldg., Shannon Room 54-134|
|Contact Name||Prof. Rob Candler|
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IBM T. J. Watson Research Center
The confluence of disruptive technologies beyond CMOS and "Big Data" workloads calls for a fundamental paradigm shift from homogenous compute-centric system to new heterogeneous data-centric system for better innovation, competition and productivity. With the objective of rethinking data-centric system design from ground up, I will first present a PCM-CMOS hardware accelerator which is inspired by the concept of ternary content addressable memory (TCAM) and enabled by emerging memory technology i.e., phase change memory (PCM). In particular, a fully-functional heterogeneous chip was designed and fabricated for the first time, achieving >10x cell area reduction compared to homogenous CMOS-based design at the same technology node. The accelerator fundamentally blurs the boundary between computation and storage, opening up tremendous opportunities for dynamic hardware specialization. It can be configured as a compute unit as either a high performance search engine with deterministic search rate or random logic to perform direct data-flow computation. It can also be configured as a storage media as high throughput storage class memory. In addition, it exploits tremendous bandwidth available on chip and puts compute close to data sources to reduce communication cost. Thus, it is an attractive solution for a wide range of data-intensive applications e.g., genome matching in bioinformatics, intrusion detection in cloud computing, etc. However, design with heterogeneous PCM/CMOS technologies poses new challenges during practical hardware prototyping due to the severely degraded signal margin introduced by technology itself. To address these challenges, I will present two enabling techniques: 1) a clocked self-referenced sensing scheme and 2) a two-bit encoding, which can also improve algorithmic mapping for better hardware utilization. With these techniques, the fabricated chip can reliably operate at very low voltage (750mV). The work was recognized as a highlighted paper by Symp. on VLSI Circuits and an invited paper for JSSC. In the second part, I will briefly highlight two techniques to move further into a more cost-effective design based on variable-bit storage. Finally, I will discuss my short-term and long-term research plans.
Dr. Jing Li is a Research Staff Member at IBM T. J. Watson Research Center. Her general research interest is developing new computing paradigm driven by either technologies or workloads or both. Her primary area of interest is VLSI design-technology interaction with a strong emphasis on “design for transformation” (rather than "design for replacement"). She has received IBM Research Division Outstanding Technical Award in 2012 for successfully achieving CEO milestone, multiple invention achievement awards from IBM from 2010-present, IBM Ph.D. Fellowship Award in 2008, Meissner Fellowship in 2004 from Purdue University, etc. She has published more than 35 technical papers in referred journals and conferences and has more than 35 patents filed/issued. She won the Best Paper Award from IEEE Circuits and Systems Society VLSI Transactions for her contribution in STT RAM. She has been reviewers for numerous journals and conferences, and has been serving on the technical committee for DAC since 2011. She also represents IBM at premier industry conference IMW as a member of Scientific/Organizing Committee. Dr. Li received PHD degree from Purdue University in 2009 and BE degree from Shanghai Jiao Tong University in 2004.