Electrical Spin Injection and Detection in Ge Nanowires and Topological Insulators
Jun 16, 2014
from 12:00 PM to 02:00 PM
|Where||Engr. IV Bldg., Tesla Room 53-125|
|Contact Name||Jianshi Tang|
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Advisor: Professor Kang L. Wang
As the major economic growth driver for decades, the continuous scaling of the feature size in the Si technology is approaching the ultimate physical limit. Novel materials and devices are in urgent need to resolve a number of critical challenges. In particular, spintronic devices have been proposed and extensively studied to potentially outperform Si devices with lower power dissipation and faster switching.
In this seminar, the carrier and spin transport in Ge nanowires will be presented. Atomic-scale thermal annealing was established as a convenient approach to make high-quality nanoscale source/drain contacts in high-performance Ge nanowire transistors. Electrical spin injection and detection in both p- and n-type Ge nanowires were demonstrated using ferromagnetic Mn5Ge3 Schottky contacts and Fe/MgO tunnel junctions, respectively. The measured spin lifetime and spin diffusion length in Ge nanowires were much larger than those reported for bulk Ge, suggesting that the spin relaxation was significantly suppressed in nanowires.
Furthermore, we studied the spin transport in topological insulators, in which the spin-momentum locking of helical surface states was preserved by the strong spin-orbit interaction and time-reversal symmetry. We demonstrated the electrical detection of the spin-polarized surface states conduction in topological insulator using a Co/Al2O3 ferromagnetic tunnel contact. Resistance hysteresis was observed when sweeping the magnetic field, and the two resistance states were reversible by changing the electric current direction. Our results showed a direct evidence of the charge current-induced spin polarization in the topological surface states. With the understanding of spin injection and detection, it might open up great opportunities to explore novel spintronic devices based on topological insulators and Ge nanowires.
Jianshi Tang is currently a Ph.D. candidate in Electrical Engineering Department at UCLA. He received his M.S. degree in Electrical Engineering from UCLA in 2010 and B.S. degree in Electronic Engineering from Tsinghua University, Beijing, China in 2008. In 2012, he was a part-time intern at Aneeve Nanotechnologies for six months. His research involves carrier and spin transport in semiconductor nanowires and novel materials for innovative device applications. He has coauthored more than 40 peer-reviewed journal papers and conference presentations. He also holds several awards including UCLA Conference Travel Grant, CESAC Scholarship, Best Poster Prize of 7th WIN Review.