Energy-efficient Design Techniques for Variation Mitigation in Next-generation Computing Systems
Mar 04, 2014
from 02:00 PM to 04:00 PM
|Where||Engr. IV Bldg., Shannon Room 54-134|
|Contact Name||Prof. Puneet Gupta|
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ARM Ltd., U.K.
Integrated circuits in modern SoCs and microprocessors are typically operated with sufficient timing margins to mitigate the impact of rising process, voltage and temperature (PVT) variations at advanced process nodes. The widening margins required to ensure robust computation inevitably leads to conservative designs with unacceptable energy-efficiency overheads. Reconciling the conflicting objectives imposed by variation-mitigation and energy-efficient computing will require fundamental departures from conventional circuit and system design practices. In my talk, I will posit error-resilient general-purpose computing as an effective approach for achieving this. I will describe how resilient techniques exploit tolerance to timing errors to automatically compensate for variations and dynamically tune a system to its most efficient operating point. I will present results from university and industrial designs that demonstrate significant efficiency improvements by combining resiliency with optimizations across algorithms, circuits and micro-architecture boundaries. I will also present directions for further research into variation-tolerant, reliable and energy-efficient system design for emerging applications in the coming decade.
Shidhartha Das received the B.Tech degree in electrical engineering from the Indian Institute of Technology, Bombay in 2002 and the M.S and Ph.D degrees in computer science and engineering from the University of Michigan, Ann Arbor in 2005 and 2009.
His research interests include micro-architectural and circuit design for variation measurement and mitigation, on-chip power delivery and VLSI architectures for digital signal processing (DSP) accelerators. His research has been featured in IEEE Spectrum and has won several awards including the Microprocessor Review analysts' choice award in innovation and best paper awards at MICRO 2003 and SAME 2010. He has authored more than 25 papers in peer-reviewed journals and conferences, including 7 invited publications. Dr. Das has 18 granted patents with several others that are pending. Currently, he is a Principal Engineer working for ARM Ltd., U.K., in the Research and Development group where he works on several aspects of low-power, variation-tolerant circuits and micro-architectural design. Dr. Das serves on the Technical Program Committee of the European Solid-State Circuits Conference (ESSCIRC 2014) and the International On-Line Testing Symposium (IOLTS 2014).