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EUV Mask Defect Avoidance and Design Implications

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What
  • Workshops
When May 28, 2014
from 12:00 PM to 01:00 PM
Where Engr. IV Bldg., Tesla Room 53-125
Contact Name
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Department Research Forum
Hosted by: Professor Mani Srivastava

Abde Ali Kagalwalla
Advisor: Prof. Puneet Gupta

 

Abstract

Extreme Ultraviolet Lithography (EUVL) is expected to play a key role in sustaining the cost per transistor benefit of semiconductor scaling. One of the key challenges facing EUVL is the defectivity of mask blanks. To mitigate mask blank defects, several defect avoidance approaches have been proposed recently. Defect avoidance uses defect locations obtained from mask blank inspection to move the design layout relative to the defective mask blank before the mask is written. In this talk, I will present a novel random walk based defect avoidance strategy that performs significantly better than the current state-of-the-art by exploring all the different degrees of freedom for avoiding defects. Although such defect avoidance techniques enable EUVL mask defect mitigation for all types of design layouts, we have found that irregular layouts are more suited to exploit these techniques. I will also describe a new metric called critical density, which can quickly evaluate the robustness of design layouts to mask defects. Critical density can be used to analyze and improve EUVL layouts during the design stage, when mask defect locations are unknown.

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