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Full Duplex Relaying with Half Duplex Relays

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What
  • Visitor Seminars
When Nov 12, 2013
from 11:00 AM to 12:00 PM
Where Engr. IV Bldg., Maxwell Room 57-124
Contact Name
Contact Phone 310-825-8885
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Giuseppe Caire

University of Southern California

 

Abstract

Full duplex relay hardware architectures have attracted a considerable attention recently. These architectures are based on some form of analog self-interference cancellation, in order to prevent the receiver to be saturated by the transmitter power. In addition, digital self-interference cancellation in the baseband takes care of the residual self-interference since analog cancellation is not perfect. Some of such proposals make use of two antennas, which are spaced and oriented appropriately such that the self-interference power entering the receiver chain is limited. Others make even use of three antennas, placed such that the transmitted signal from two antennas cancel each other at the third antenna, used by the receiver.

In this work, we study a ``virtual'' full-duplex relay scheme constructed by two half-duplex relays. This can be seen (to some extent) as the distributed version of full-duplex proposals based on multiple antennas). At each time slot, alternatively, one of relays (in reception mode) receives a new data from the source while the other relay (in transmission mode) forwards the processed data (obtained in the previous time slot) to the destination. This relaying operation is known as “successive relaying”. It is interesting to notice that the topology is identical to the well-known diamond relay network, with the addition of one interfering link between the two relays. The main performance bottleneck of successive relaying is the so-called inter-relay interference that corresponds to the self-interference in full-duplex relays. In this talk, we examine several information theoretic schemes and their achievable rates for successive relaying. Then, we generalize successive relaying to multihop virtual full-duplex relay channels. We shall discuss relative merits and implementation drawbacks of the various schemes, and compare them in terms of their achievable rate.

 

Biography

Giuseppe Caire received the B.Sc. in Electrical Engineering from Politecnico di Torino (Italy), in 1990, the M.Sc. in Electrical Engineering from Princeton University in 1992 and the Ph.D. from Politecnico di Torino in 1994.  He is currently a professor of Electrical Engineering with the Viterbi School of Engineering, University of Southern California, Los Angeles, CA. Giuseppe Caire is Fellow of IEEE since 2005. He has served in the Board of Governors of the IEEE Information Theory Society from 2004 to 2007 and as President of the IEEE Information Theory Society in 2011. His main research interests are in the field of communications theory, information theory, channel and source coding with particular focus on wireless communications.

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