Silicon IC Technology Innovations and Challenges
Mar 10, 2014
from 12:30 PM to 02:00 PM
|Where||Engr. IV Bldg., Shannon Room 54-134|
|Contact Name||Prof. Jason Woo|
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The scaling of the silicon IC technology provides improved circuit performance, higher density, and lower cost. The most advanced silicon IC technology today allows billions of transistors to be built on a piece of silicon substrate approximately 1cm2 in area and connected by more than ten layers of metals with minimum width tens of nano-meters. The innovations enable this to happen will be reviewed in areas of lithography, transistors, and interconnects. As the technology is getting more complicated, the manufacturing cost of continuing scaling increased more rapidly than it did in the past. In addition, the power constraint begins to limit the circuit speed as billions of transistors were packed in a single chip. The conventional way of scaling the silicon IC technology can no longer provide the same level of performance and cost improvements as it used to. Some cost and profit structures and a new scaling paradigm, system level scaling, will be discussed.
Shang-yi Chiang earned his Bachelor of Science degree from National Taiwan University in 1968, his Master of Science degree from Princeton University in 1970, and his Doctorate from Stanford University in 1974, all in electrical engineering. After completing his studies, he worked at ITT Corporation, Texas Instruments, and Hewlett-Packard. He returned to Taiwan in 1997 to serve as TSMC’s Vice President of Research and Development, Senior Vice President of R&D as well as Executive Vice President and Co-Chief Operating Officer before announcing his retirement in October of 2013.
During Shang-yi’s 40-year career in the semiconductor industry, he has contributed to the research and development of CMOS, NMOS, Bipolar, DMOS, SOS, SOI, GaAs lasers, LED, E-Beam lithography, and silicon solar cells. At TSMC, his R&D team set milestones in semiconductor technology in the 0.25 micron, 0.18 micron, 0.15 micron, 0.13 micron, 90nm, 65nm, and 40nm generations, and continue to extend to the 28nm, 20nm, and 16FinFET generations. Under his leadership, TSMC rose to become a semiconductor technology leader with its R&D organization growing from 148 to 4,000 people, while annual R&D spending rising from $80 million to $1.6 billion.