Voltage-Controlled Magnetic Dynamics in Nanoscale Magnetic Tunnel Junctions
May 28, 2014
from 02:00 PM to 04:00 PM
|Where||Engr. IV Bldg., Faraday Room 67-124|
|Contact Name||Juan G. Alzate|
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Juan G. Alzate
Advisor: Prof. Kang L. Wang
Spintronic devices, i.e., those utilizing the interaction of magnetic moments with electric voltages and currents in magnetic nanostructures, offer an exceptionally promising set of candidates for future electronic memory needs. Recently, the possibility of reversing the magnetization of nanoscale magnetic tunnel junction (MTJ) devices using the spin transfer torque (STT) effect has attracted the attention of industry and academia, since STT-MRAM has been demonstrated to be a strong candidate for a high speed, high density, and high endurance nonvolatile memory. Further, by replacing the current-driven (e.g., STT) switching mechanism for a voltage-controlled effect, a novel magnetoelectric RAM (MeRAM) architecture could result in considerable improvements in terms of density and dissipated energy during switching, both factors which are limited in STT-MRAM by the large currents required.
In this talk, the possibility of exploiting the voltage-controlled magnetic anisotropy (VCMA) effect on nanoscale MTJ devices as the driving mechanism for MeRAM will be introduced. Experimental results on the demonstration of current-assisted and purely voltage-controlled switching in the thermally-activated and precessional regimes are presented. The advantages and challenges of this voltage-driven approach will be discussed while validating, via simulations calibrated against experimental parameters, the possibility of achieving low write error rates in these memory bits. Finally, a detailed characterization of the voltage-driven dynamics in these devices will be shown. This will include experimental results on the accurate characterization of the temperature dependence of the perpendicular anisotropy and the VCMA effect, as well as on the influence of higher order anisotropies over MTJ dynamics measured via ferromagnetic resonance (FMR).
Juan G. Alzate received his B.S. in Electronics Engineering and his B.S. in Physics (both Summa Cum Laude) from Universidad de Los Andes, Bogota, Colombia, in 2007, and his M.S. in Electrical Engineering from UCLA in 2011, where he is currently a Ph.D. candidate in the Device Research Laboratory (DRL) under the supervision of Prof. Kang L. Wang. During the summer of 2010, he was a Graduate Research Intern at the Components Research group in Intel Corporation. He holds several awards including the Qualcomm Innovation Fellowship, Best Poster Award in the 6th IEEE Magnetics Summer School in 2013, and is a finalist for Best Student Paper Award in the IEEE International Conference on Magnetism (Intermag 2014). His current research is focused on magnetic memory and logic devices, but he has a broad interest in emerging nanoelectronic and nanomagnetic devices, as well as in novel devices, materials and systems for CMOS-based and beyond classical CMOS scaling computation.