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Prof. Markovic selected to receive 2009 NSF CAREER Award

January 2009

Assistant Professor Dejan Markovic has been selected to receive the 2009 NSF CAREER Award from the National Science Foundation. The Faculty Early Career Development (CAREER) Program is a Foundation-wide activity that offers the National Science Foundation's most prestigious awards in support of junior faculty who exemplify the role of teacher-scholars through outstanding research, excellent education and the integration of education and research within the context of the mission of their organizations. Professor Markovic's award recognizes his career development plan entitled "Area-and-Power-Minimized Many-Channel Neural-Spike DSP". The abstract for the project appears below.

Professor Dejan Markovic joined the department in July 2006. He received his Ph.D. in Electrical Engineering from UC Berkeley in 2006, where he was a member of the Berkeley Wireless Research Center. Prof. Markovic's research focuses on rapid prototyping and optimization of power limited digital systems, with emphasis on the next generation wireless communication devices. Topics include digital integrated circuits, power/area-efficient VLSI signal processing architectures, optimization methods, and supporting design automation environments.

Abstract
NSF CAREER Award (Markovic): Area-and-Power-Minimized Many-Channel Neural-Spike DSP

The objective of this research is to revolutionize the digital-signal-processing (DSP) technology used for many-channel electrophysiological recording systems used in both clinical and neuroscientific applications. The approach is to make a tight interaction between algorithms and the underlying technology to optimize the DSP architecture. Improvements by several orders of magnitude in the increased number of channels and decreased hardware cost will be demonstrated.

This project will demonstrate a real-time implantable DSP chip scalable up to 2,000 neural channels. Existing designs provide partial DSP functionality for only up to 30 channels. The chip will be able to isolate activity from individual neurons and reduce the data rate below 800 kbps while maintaining a power density less than 0.8 mW/mm2, as required by safety regulations. The project will also provide a DSP architecture for hardware emulation to demonstrate over a 10,000 times speed-up in data processing compared to state-of-the-art computers.

A successful integration of neural-data processing will significantly advance many applications such as visual, auditory, motor, and cognitive prosthetics. Methods for achieving faster analysis of electrophysiological data will provide neuroscientists quicker access to important research data and improve the overall quality of living. The program intends to train a diverse population of students for careers in industry and academia through relevant and practical design projects, and promote a wider public access to the latest research and educational tools. The far-reaching social and economic impact will be to help sustain the spread and evolution of information technology to new biological and medical applications.

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