Primary Area: Circuits & Embedded Systems
Office: 6730C Boelter Hall
Phone: (310) 825-1376
Personal Web: http://www.seas.ucla.edu/~puneet
Research Lab: Research Lab:
Research and Teaching Interests:
Design-technology co-optimization, physical design, variability and reliability aware computer architectures
|Awards and Recognitions|
|2012||IBM Faculty Award|
|2010||ACM/SIGDA Outstanding New Faculty Award|
|2009||SRC Inventor Recognition Award|
|2009||NSF Faculty Early Career Development (CAREER) Award|
|2007||European Design Automation Association (EDAA) Outstanding Dissertation Award|
|2004||IBM Ph.D. Fellowship|
- M. Gottscho, L. A. D. Bathen, N. Dutt, A. Nicolau, and P. Gupta, “ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings,” *IEEE Transactions on Computers*, 2014.
- L. Lai, V. Chandra, R. Aitken, and P. Gupta, “SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology,” *IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, vol. 33, pp. 1168-1179, Aug 2014.
- A.A. Kagalwalla and P. Gupta, “Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects,” *SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)*, vol. 13, no. 4, p. 043005, 2014.
- R.S. Ghaida and P. Gupta, “DRE: a Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies,” *IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, 2012.
- P.Gupta, Y. Agarwal, L. Dolecek, N. Dutt, R. K. Gupta, R. Kumar, S. Mitra, A. N. T. S. Rosing, M. B. Srivastava, S. Swanson, and D. Sylvester, “Underdesigned and opportunistic computing in presence of hardware variability,” *IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, 2012. Keynote Paper.
- T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Wafer Manufacturing and Test Cost Reduction,” *IEEE Transactions on Semiconductor Manufacturing*, 2012.
- W.-C. Wang and P. Gupta, “Efficient Layout Generation and Evaluation of Vertical Channel Devices,” in *Proc. IEEE/ACM International Conference on Computer-Aided Design*, November 2014.