Puneet Gupta

Puneet Gupta

Puneet Gupta
Associate Professor
Primary Area: Circuits & Embedded Systems

Office: 6730C Boelter Hall
Phone: (310) 825-1376
Personal Web: http://www.seas.ucla.edu/~puneet
Research Lab: Research Lab:NanoCAD Laboratory

Research and Teaching Interests:
Design-technology co-optimization, physical design, variability and reliability aware computer architectures


Awards and Recognitions
2012 IBM Faculty Award
2010 ACM/SIGDA Outstanding New Faculty Award
2009 SRC Inventor Recognition Award
2009 NSF Faculty Early Career Development (CAREER) Award
2007 European Design Automation Association (EDAA) Outstanding Dissertation Award
2004 IBM Ph.D. Fellowship


Selected Publications
  • W.-C. Wang, Y. Yona, S. Diggavi, and P. Gupta, “LEDPUF: Stability-Guaranteed Physical Unclonable Functions through Locally Enhanced Defectivity,” in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2016.
  • W.-C. Wang and P. Gupta, “Efficient Layout Generation and Evaluation of Vertical Channel Devices,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016.
  • M. Gottscho, C. Schoeny, L. Dolecek, and P. Gupta, “Software-Defined Error-Correcting Codes,” in IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), June 2016.
  • Y. Badr, A. Torres, and P. Gupta, “Mask Assignment and Synthesis of DSA-MP Hybrid Lithography for sub-7nm Contacts/Vias,” in Proc. ACM/IEEE Design Automation Conference, June 2015.
  • M. Gottscho, A. BanaiyanMofrad, N. Dutt, A. Nicolau, and P. Gupta, “DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale Era,” ACM Transactions on Architecture and Code Optimization (TACO), vol. 12, August 2015.
  • L. Lai, V. Chandra, R. Aitken, and P. Gupta, “SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology,” *IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, vol. 33, pp. 1168-1179, Aug 2014.
  • A.A. Kagalwalla and P. Gupta, “Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects,” *SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)*, vol. 13, no. 4, p. 043005, 2014.
  • R.S. Ghaida and P. Gupta, “DRE: a Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies,” *IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, 2012.
  • P.Gupta, Y. Agarwal, L. Dolecek, N. Dutt, R. K. Gupta, R. Kumar, S. Mitra, A. N. T. S. Rosing, M. B. Srivastava, S. Swanson, and D. Sylvester, “Underdesigned and opportunistic computing in presence of hardware variability,” *IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, 2012. Keynote Paper.